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參數資料
| 型號： | TS68302VR16 |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Integrated Multiprotocol Processor IMP |
| 中文描述： | 16-BIT, 16.67 MHz, RISC MICROCONTROLLER, CPGA132 |
| 封裝： | CERAMIC, PGA-132 |
| 文件頁數： | 13/47頁 |
| 文件大?。?/td> | 1149K |
| 代理商： | TS68302VR16 |
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13
TS68302
2117A–HIREL–11/02
Table 8.
AC Electrical Specifications
IMP Bus Master Cycles (see Figure 7, Figure 8 and Figure 9) f = 16.67 MHz
Num.
Symbol
Parameter
Min
Max
Unit
6
t
CHFCADV
Clock high to FC, address valid
45
ns
7
t
CHADZ
Clock high to address, data bus high impedance (maximum)
50
ns
8
t
CHAFI
Clock high to address, FC invalid (minimum)
0
ns
9
t
CHSL
Clock high to AS, DS asserted
(1)
3
30
ns
11
t
AFCVSL
Address, FC valid to AS, DS asserted (read)/AS asserted
(write)
(2)
15
ns
12
t
CLSH
Clock low to AS, DS negated
(1)
30
ns
13
t
SHAFI
AS, DS negated to address, FC invalid
(2)
15
ns
14
t
SL
AS (and DS read) width asserted
(2)
120
ns
14A
t
DSL
DS width asserted, write
(2)
60
ns
15
t
SH
AS, DS width negated
(2)
60
ns
16
t
CHCZ
Clock high to control bus high impedance
50
ns
17
t
SHRH
AS, DS negated to R/W invalid
(2)
15
ns
18
t
CHRH
Clock high to R/W high
(1)
30
ns
20
t
CHRL
Clock high to R/W low
(1)
30
ns
20A
t
ASRV
AS asserted to R/W low (write)
(2)(3)
10
ns
21
t
AFCVRL
Address FC valid to R/W low (write)
(2)
15
ns
22
t
RLSL
R/W low to DS asserted (write)
(2)
30
ns
23
t
CLDO
Clock low to data-out valid
30
ns
25
t
SHDOI
AS, DS, negated to data-out invalid (write)
(2)
15
ns
26
t
DOSL
Data-out valid to DS asserted (write)
(2)
15
ns
27
t
DICL
Data-in valid to clock low (Setup time on read)
(4)
7
ns
28
t
SHDAH
AS, DS negated to DTACK negated (asynchronous hold)
(2)
0
110
ns
29
t
SHDII
AS, DS negated to data-in invalid (hold time on read)
0
ns
30
t
SHBEH
AS, DS negated to BEER negated
0
ns
31
t
DALDI
DTACK asserted to data-in valid (setup time)
(2)(4)
50
ns
32
t
RHr
, t
RHf
HALT and RESET input transition time
150
ns
33
t
CHGL
Clock high to BG asserted
30
ns
34
t
CHGH
Clock high to BG negated
30
ns
35
t
BRLGL
BR asserted to BG asserted
2.5
4.5
clks
36
t
BRHGH
BR negated to BG negated
(5)
1.5
2.5
clks
37
t
GALGH
BGACK asserted to BG negated
2.5
4.5
clks
37A
t
GALBRH
BGACK asserted to BG negated
(6)
10
1.5
ns/clks
38
t
GLZ
BG asserted to control, address, data bus high impedance
(AS negated)
50
ns
39
t
GH
BG width negated
1.5
clks
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