參數(shù)資料
型號： TS80C51RD2-LCE
廠商： Atmel
文件頁數(shù)： 79/84頁
文件大?。?/td> 0K
描述： IC MCU 8BIT 768BYTE 30MHZ 44VQFP
標(biāo)準(zhǔn)包裝： 800
系列： 80C
核心處理器： 8051
芯體尺寸： 8-位
速度： 30/20MHz
連通性： UART/USART
外圍設(shè)備： POR，PWM，WDT
輸入/輸出數(shù)： 32
程序存儲(chǔ)器類型： ROMless
RAM 容量： 768 x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 5.5 V
振蕩器型： 內(nèi)部
工作溫度： 0°C ~ 70°C
封裝/外殼： 44-QFP
包裝： 托盤
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
DS70292G-page 82
2007-2012 Microchip Technology Inc.
FIGURE 6-2:
SYSTEM RESET TIMING
Reset
Run
Device Status
VDD
VPOR
Vbor
VBOR
POR
BOR
SYSRST
TPWRT
TPOR
TBOR
Oscillator Clock
TOSCD
TOST
TLOCK
Time
FSCM
TFSCM
1
2
3
4
5
6
Note 1: POR: A POR circuit holds the device in Reset when the power supply is turned on. The POR circuit is active
until VDD crosses the VPOR threshold and the delay TPOR has elapsed.
2: BOR: The on-chip voltage regulator has a BOR circuit that keeps the device in Reset until VDD crosses the
VBOR threshold and the delay TBOR has elapsed. The delay TBOR ensures the voltage regulator output
becomes stable.
3: PWRT Timer: The programmable power-up timer continues to hold the processor in Reset for a specific
period of time (TPWRT) after a BOR. The delay TPWRT ensures that the system power supplies have stabilized
at the appropriate level for full-speed operation. After the delay TPWRT has elapsed, the SYSRST becomes
inactive, which in turn enables the selected oscillator to start generating clock cycles.
4: Oscillator Delay: The total delay for the clock to be ready for various clock source selections are given in
5: When the oscillator clock is ready, the processor begins execution from location 0x000000. The user
application programs a GOTO instruction at the reset address, which redirects program execution to the
appropriate start-up routine.
6: The Fail-Safe Clock Monitor (FSCM), if enabled, begins to monitor the system clock when the system clock
is ready and the delay TFSCM elapsed.
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