參數(shù)資料
型號： TS80C51RD2-LCE
廠商： Atmel
文件頁數(shù)： 84/84頁
文件大?。?/td> 0K
描述： IC MCU 8BIT 768BYTE 30MHZ 44VQFP
標準包裝： 800
系列： 80C
核心處理器： 8051
芯體尺寸： 8-位
速度： 30/20MHz
連通性： UART/USART
外圍設備： POR，PWM，WDT
輸入/輸出數(shù)： 32
程序存儲器類型： ROMless
RAM 容量： 768 x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 5.5 V
振蕩器型： 內(nèi)部
工作溫度： 0°C ~ 70°C
封裝/外殼： 44-QFP
包裝： 托盤
9
4188F–8051–01/08
AT/TS8xC51Rx2
5.1
Pin Description for 64/68 pin Packages
Port 4 and Port 5 are 8-bit bidirectional I/O ports with internal pull-ups. Pins that have 1s written
to them are pulled high by the internal pull ups and can be used as inputs.
As inputs, pins that are externally pulled low will source current because of the internal pull-ups.
Refer to the previous pin description for other pins.
Table 5-1.
64/68 Pin Packages Configuration
12
14
8
I
INT0 (P3.2): External interrupt 0
13
15
9
I
INT1 (P3.3): External interrupt 1
14
16
10
I
T0 (P3.4): Timer 0 external input
15
17
11
I
T1 (P3.5): Timer 1 external input
16
18
12
O
WR (P3.6): External data memory write strobe
17
19
13
O
RD (P3.7): External data memory read strobe
Reset
9
10
4
I
Reset: A high on this pin for two machine cycles while the oscillator is running, resets
the device. An internal diffused resistor to VSS permits a power-on reset using only an
external capacitor to VCC. If the hardware watchdog reaches its time-out, the reset pin
becomes an output during the time the internal reset is activated.
ALE/PROG
30
33
27
O (I)
Address Latch Enable/Program Pulse: Output pulse for latching the low byte of the
address during an access to external memory. In normal operation, ALE is emitted at a
constant rate of 1/6 (1/3 in X2 mode) the oscillator frequency, and can be used for
external timing or clocking. Note that one ALE pulse is skipped during each access to
external data memory. This pin is also the program pulse input (PROG) during EPROM
programming. ALE can be disabled by setting SFR’s AUXR.0 bit. With this bit set, ALE
will be inactive during internal fetches.
PSEN
29
32
26
O
Program Store ENable: The read strobe to external program memory. When
executing code from the external program memory, PSEN is activated twice each
machine cycle, except that two PSEN activations are skipped during each access to
external data memory. PSEN is not activated during fetches from internal program
memory.
EA/VPP
31
35
29
I
External Access Enable/Programming Supply Voltage: EA must be externally held
low to enable the device to fetch code from external program memory locations 0000H
and 3FFFH (RB) or 7FFFH (RC), or FFFFH (RD). If EA is held high, the device
executes from internal program memory unless the program counter contains an
address greater than 3FFFH (RB) or 7FFFH (RC) EA must be held low for ROMless
devices. This pin also receives the 12.75V programming supply voltage (VPP) during
EPROM programming. If security level 1 is programmed, EA will be internally latched
on Reset.
XTAL1
19
21
15
I
Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock
generator circuits.
XTAL2
18
20
14
O
Crystal 2: Output from the inverting oscillator amplifier
Mnemonic
Pin Number
Type
Name And Function
DIL
LCC
VQFP 1.4
Pin
PLCC68
SQUARE VQFP64 1.4
VSS
51
9/40
VCC
17
8
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