參數(shù)資料
型號： TS80C51RD2-LCE
廠商： Atmel
文件頁數(shù)： 81/84頁
文件大?。?/td> 0K
描述： IC MCU 8BIT 768BYTE 30MHZ 44VQFP
標準包裝： 800
系列： 80C
核心處理器： 8051
芯體尺寸： 8-位
速度： 30/20MHz
連通性： UART/USART
外圍設備： POR，PWM，WDT
輸入/輸出數(shù)： 32
程序存儲器類型： ROMless
RAM 容量： 768 x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 5.5 V
振蕩器型： 內(nèi)部
工作溫度： 0°C ~ 70°C
封裝/外殼： 44-QFP
包裝： 托盤
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
DS70292G-page 84
2007-2012 Microchip Technology Inc.
FIGURE 6-3:
BROWN-OUT SITUATIONS
6.5
External Reset (EXTR)
The external Reset is generated by driving the MCLR
pin low. The MCLR pin is a Schmitt trigger input with an
additional glitch filter. Reset pulses that are longer than
the minimum pulse-width will generate a Reset. Refer
minimum pulse-width specifications. The External
Reset (MCLR) Pin (EXTR) bit in the Reset Control
register (RCON) is set to indicate the MCLR Reset.
6.5.0.1
EXTERNAL SUPERVISORY CIRCUIT
Many systems have external supervisory circuits that
generate reset signals to Reset multiple devices in the
system. This external Reset signal can be directly con-
nected to the MCLR pin to Reset the device when the
rest of system is Reset.
6.5.0.2
INTERNAL SUPERVISORY CIRCUIT
When using the internal power supervisory circuit to
Reset the device, the external reset pin (MCLR) should
be tied directly or resistively to VDD. In this case, the
MCLR pin will not be used to generate a Reset. The
external reset pin (MCLR) does not have an internal
pull-up and must not be left unconnected.
6.6
Software RESET Instruction (SWR)
Whenever the RESET instruction is executed, the
device will assert SYSRST, placing the device in a
special Reset state. This Reset state will not re-
initialize the clock. The clock source in effect prior to the
RESET instruction will remain. SYSRST is released at
the next instruction cycle, and the reset vector fetch will
commence.
The Software Reset (Instruction) Flag (SWR) bit in the
Reset Control (RCON<6>) register is set to indicate
the software Reset.
6.7
Watchdog Time-out Reset (WDTO)
Whenever a Watchdog time-out occurs, the device will
asynchronously assert SYSRST. The clock source will
remain unchanged. A WDT time-out during Sleep or
Idle mode will wake-up the processor, but will not reset
the processor.
The Watchdog Timer Time-out Flag (WDTO) bit in the
Reset Control register (RCON<4>) is set to indicate
the
Watchdog
Reset.
Refer
to
“Watchdog Timer (WDT)” for more information on
Watchdog Reset.
6.8
Trap Conflict Reset
If a lower-priority hard trap occurs while a higher-prior-
ity trap is being processed, a hard trap conflict Reset
occurs. The hard traps include exceptions of priority
level 13 through level 15, inclusive. The address error
(level 13) and oscillator error (level 14) traps fall into
this category.
The Trap Reset Flag (TRAPR) bit in the Reset Control
register (RCON<15>) is set to indicate the Trap Conflict
more information on trap conflict Resets.
VDD
SYSRST
VBOR
VDD
SYSRST
VBOR
VDD
SYSRST
VBOR
TBOR + TPWRT
VDD dips before PWRT expires
TBOR + TPWRT
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