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參數(shù)資料
| 型號： | TS80L188EC-13 |
| 元件分類： | 16位微控制器 |
| 英文描述： | 16-Bit Microprocessor |
| 中文描述： | 16位微處理器 |
| 文件頁數(shù)： | 12/57頁 |
| 文件大?。?/td> | 585K |
| 代理商： | TS80L188EC-13 |
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80C186EC/188EC, 80L186EC/188EC
Table 2. Pin Descriptions
(Continued)
Pin Name
Pin
Type
Input
Type
Output
States
Pin Description
RD
O
D
H(Z)
R(Z)
I(1)
P(1)
ReaD
output signals that the accessed memory or I/O
device should drive data information onto the data bus.
WR
O
D
H(Z)
R(Z)
I(1)
P(1)
WRite
output signals that data available on the data bus are
to be written into the accessed memory or I/O device.
READY
I
A(L)
S(L)
(Note 1)
D
READY
input to signal the completion of a bus cycle. READY
must be active to terminate any 80C186EC bus cycle, unless
it is ignored by correctly programming the Chip-Select unit.
DEN
O
D
H(Z)
R(Z)
I(1)
P(1)
Data ENable
output to control the enable of bi-directional
transceivers in a buffered system. DEN is active only when
data is to be transferred on the bus.
DT/R
O
D
H(Z)
R(Z)
I(X)
P(X)
Data Transmit/Receive
output controls the direction of a bi-
directional buffer in a buffered system.
LOCK
I/O
A(L)
H(Z)
R(Z)
I(X)
P(X)
LOCK
output indicates that the bus cycle in progress is not
interruptable. The processor will not service other bus
requests (such as HOLD) while LOCK is active. This pin is
configured as a weakly held high input while RESIN is active
and must not be driven low.
HOLD
I
A(L)
D
HOLD
request input to signal that an external bus master
wishes to gain control of the local bus. The processor will
relinquish control of the local bus between instruction
boundaries that are not LOCKed.
HLDA
O
D
H(1)
R(0)
I(0)
P(0)
HoLD Acknowledge
output to indicate that the processor
has relinquished control of the local bus. When HLDA is
asserted, the processor will (or has) floated its data bus and
control signals allowing another bus master to drive the
signals directly.
NCS
O
D
H(1)
R(1)
I(1)
P(1)
Numerics Coprocessor Select
output is generated when
acessing a numerics coprocessor. This signal does not exist
on the 80C188EC/80L188EC.
ERROR
I
A(L)
D
ERROR
input that indicates the last numerics processor
extension operation resulted in an exception condition. An
interrupt TYPE 16 is generated if ERROR is sampled active
at the beginning of a numerics operation. Systems not using
an 80C187 must tie ERROR to V
CC
. This signal does not
exist on the 80C188EC/80L188EC.
NOTE:
Pin names in parentheses apply to the 80C188EC/80L188EC.
12
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