1999 Oct 05
2
Philips Semiconductors
Preliminary specification
2.7 GHz I
2
C-bus controlled low phase
noise frequency synthesizer
TSA5059
FEATURES
Complete 2.7 GHz single chip system
Optimized for low phase noise
Selectable divide-by-two prescaler
Operation up to 2.7 GHz with and without divide-by-two
prescaler
Selectable reference divider ratio
Compatible with UK-DTT (Digital Terrestrial Television)
offset requirements
Selectable crystal/comparison frequency output
Four selectable charge pump currents
Four selectable I
2
C-bus addresses
Standard and fast mode I
2
C-bus
I
2
C-bus compatible with 3.3 and 5 V microcontrollers
5-level Analog-to-Digital Converter (ADC)
Low power consumption
33 V tuning voltage drive
Three I/O ports and one output port.
APPLICATIONS
SAT, TV, VCR and cable tuning systems
Digital set-top boxes.
GENERAL DESCRIPTION
The TSA5059 is a single chip PLL frequency synthesizer
designed for satellite and terrestrial tuning systems up to
2.7 GHz.
TheRFpreamplifierdrivesthe17-bitmaindividerenabling
a step size equal to the comparison frequency, for an input
frequency up to 2.7 GHz. A fixed divide-by-two additional
prescaler can be inserted between the preamplifier and
the main divider to give a software compatibility with
existing ICs. In this case, the step size is twice the
comparison frequency.
The comparison frequency is obtained from an on-chip
crystal oscillator that can also be driven from an external
source. Either the crystal frequency or the comparison
frequency can be switched to the XT/COMP output pin to
drive the reference input of another synthesizer or the
clock input of a digital demodulation IC.
Bothdividedandcomparisonfrequencyarecomparedinto
the fast phase detector which drives the charge pump.
The loop amplifier is also on-chip, including the
high-voltage transistor to drive directly the 33 V tuning
voltage, without the need of an external transistor.
ControldataisenteredviatheI
2
C-bus;fiveserialbytesare
required to address the device, select the main divider
ratio, the reference divider ratio, program the four output
ports, set the charge pump current, select the prescaler by
two, select the signal to switch to the XT/COMP output pin
and/or select a specific test mode. Three of the four output
ports can also be used as input ports and a 5-level ADC is
provided. Digital information concerning the input ports
and the ADC can be read out of the TSA5059 on the SDA
line (one status byte) during a READ operation. A flag is
set when the loop is ‘in-lock’ and is read during a READ
operation, as well as the Power-on reset flag. The device
has four programmable addresses, programmed by
applying a specific voltage at pin AS, enabling the use of
multiple synthesizers in the same system.