參數(shù)資料
型號: TSA5060A
廠商: NXP Semiconductors N.V.
英文描述: 1.3 GHz I2C-bus controlled low phase noise frequency synthesizer
中文描述: 1.3千兆赫的I2C控制的低相位噪聲頻率合成器總線
文件頁數(shù): 2/24頁
文件大?。?/td> 119K
代理商: TSA5060A
2000 Oct 24
2
Philips Semiconductors
Product specification
1.3 GHz I
2
C-bus controlled low phase
noise frequency synthesizer
TSA5060A
FEATURES
Complete 1.3 GHz single chip system
Optimized for low phase noise
Selectable divide-by-two prescaler
Operationupto1.3 GHzwithoutdivide-by-twoprescaler
Selectable reference divider ratio
Compatible with UK-DTT (Digital Terrestrial Television)
offset requirements
Selectable crystal or comparison frequency output
Four selectable charge pump currents
Four selectable I
2
C-bus addresses
Standard and fast mode I
2
C-bus
I
2
C-bus compatible with 3.3 and 5 V microcontrollers
5-level Analog-to-Digital Converter (ADC)
Low power consumption
Three I/O ports and one output port.
APPLICATIONS
Digital terrestrial and cable tuning systems
Hybrid (digital and analog) terrestrial and cable tuning
systems
Digital set-top boxes.
GENERAL DESCRIPTION
The TSA5060A is a single chip PLL frequency synthesizer
designed for terrestrial and cable tuning systems up to
1.3 GHz.
TheRF preamplifierdrivesthe17-bitmaindividerenabling
a step size equal to the comparison frequency, for an input
frequency up to 1.3 GHz covering the complete terrestrial
frequency range. A fixed divide-by-two additional
prescaler can be inserted between the preamplifier and
the main divider. In this case, the step size is twice the
comparison frequency.
The comparison frequency is obtained from an on-chip
crystal oscillator that can also be driven from an external
source. Either the crystal frequency or the comparison
frequency can be switched to the XT/COMP output pin to
drive the reference input of another synthesizer or the
clock input of a digital demodulation IC.
Bothdivided and comparison frequencies are compared in
the fast phase detector which drives the charge pump.
The loop amplifier is also on-chip, however an external
NPN transistor to drive directly the 33 V tuning voltage.
ControldataisenteredviatheI
2
C-bus;fiveserialbytesare
required to address the device, select the main divider
ratio, the reference divider ratio, program the four output
ports, set the charge pump current, select the prescaler by
two, select the signal to switch to the XT/COMP output pin
and select a specific test mode. Three of the four output
ports can also be used as input ports and a 5-level ADC is
provided. Digital information concerning the input ports
and the ADC canbe readout of the TSA5060A onthe SDA
line (one status byte) during a READ operation. A flag is
set when the loop is ‘in-lock’ and is read during a READ
operation, as well as the Power-on reset flag. The device
has four programmable addresses, programmed by
applying a specific voltage at pin AS, enabling the use of
multiple synthesizers in the same system.
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