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參數(shù)資料
| 型號： | TSB12LV22PZP |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | OHCI-Lynx PCI-BASED IEEE 1394 HOST CONTROLLER |
| 中文描述： | OHCI的山貓基于PCI的1394主控制器 |
| 文件頁數(shù)： | 24/106頁 |
| 文件大?。?/td> | 605K |
| 代理商： | TSB12LV22PZP |
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2
–
8
BIT
NUMBER
DESCRIPTION
DIR
FUNCTION
BIT NAME
20
CYMAS
Cycle Master
R/W
When CYMAS is set and the TSB12LV32 is attached to the
root Phy, the cyclemaster function is enabled. When the
cycle_count field of the cycle timer register increments, the
transmitter sends a cycle-start packet.
21
CYSRC
Cycle Source
R/W
When CYSRC is set, the cycle_count field increments and
the cycle_offset field resets for each positive transition of
CYCLEIN. When CYSRC is cleared, the cycle_count field
increments when the cycle_offset field rolls over.
22
CYTEN
Cycle timer
enable
R/W
When CYTEN is set, the cycle_offset field increments.
23
CLRSIDER
Self-ID
error-code
clear
W
When CLRSIDER is set, the SIDERCODE field (bits 24
–
27)
is cleared.This bit clears itself.
24
–
27
SIDERCODE
Self-ID error
code
R
SIDERCODE contains the error code of the first Self-ID
Error. The error code is as follows:
0000
No error
0001
Last self-ID received was not all child ports
0010
Received Phy ID in self-ID not as expected
0011
Quadlet not inverted (phase error)
0100
Phy ID sequence error (two or more gaps in IDs)
0101
Phy ID sequence error (large gap in IDs)
0110
Phy ID error within packet
0111
Quadlet not the inversion of the prior quadlet
1000
Reserved
28
CMAUTO
Auto set cycle
master
R/W
When CMAUTO is high, the TSB12LV32 automatically
enables CYMAS when the this node becomes the root
following a bus reset.
29
IRP1EN
IR port 1
enable
R/W
When IRP1EN is set, the receiver accepts isochronous
packets when the channel number matches the value in the
IR port1 field at18h
30
IRP2EN
IR port 2
enable
R/W
When IRP2EN is set, the receiver accepts isochronous
packets when the channel number matches the value in the
IR Port2 field at18h
31
RESERVED
Reserved
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相關代理商/技術參數(shù) |
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