參數(shù)資料
型號: TSB43AA82A1
廠商: Texas Instruments, Inc.
英文描述: 1394 integrated PHY and link layer controller(1394集成PHY和鏈路層控制器)
中文描述: 1394綜合物理層和鏈路層控制器(1394集成物理層和鏈路層控制器)
文件頁數(shù): 106/146頁
文件大?。?/td> 597K
代理商: TSB43AA82A1
96
9.3.3
Figure 92 shows the SCSI handshake mode expanded to better show signal timing. Table 93 shows timing values
for Figure 92.
Timing Values (Modes E and H)
BDREQ
BDACK
BDIF[2:0]
BDIO[15:0](IN)
tsu(BD)
th(BD)
td(ACKHREQL)
BDWR/RD
BDOF[2:0]
BDIO[15:0](OUT)
td(ACKHRWH)
tsu(BD)
th(BD)
ta(OEN)
TA(OEN)
tdis(OEN)
tdis(OEN)
td(ACKLREQH)
td(RWLACKL)
tw(RD/WR/ACK)
tw(RD/WR/ACK)
NOTE: td(ACKHREQL) is the duration from when both BDACK and BDWR / BDRD are asserted (rising edge) until BDREQ is negated (falling edge).
td(ACKLREQH) is the duration from when both BDACK and BDWR / BDRD are negated (falling edge) until BDREQ is asserted (rising edge).
Figure 92. SCSI Handshake Mode
Table 93. SCSI Handshake Mode
ITEM
TITLE
MIN
MAX
UNIT
td(ACKHREQL)
td(ACKLREQH)
BDREQ delay 0
2
11
ns
BDREQ delay 1
2
62-tw(RD/WR/ACK)
(>11) or 11
ns
td(ACKHRWH)
td(RWLACKL)
tsu(BD)
th(BD)
tA(OEN)
ta(OEN)
tdis(OEN)
tw(RD/WR/ACK)
BDACK to BRWR/RD
0
ns
BRWR/RD to BDACK
0
ns
SCSI data input setup
7
ns
SCSI data input hold
0
ns
SCSI data flag invalid
1
14
ns
SCSI data output enable
1
14
ns
SCSI data output disable
1
14
ns
BDRD/BDWR/BDACK active width
22
ns
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