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參數(shù)資料
| 型號： | TSB43AA82A1 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 1394 integrated PHY and link layer controller(1394集成PHY和鏈路層控制器) |
| 中文描述： | 1394綜合物理層和鏈路層控制器（1394集成物理層和鏈路層控制器） |
| 文件頁數(shù)： | 23/146頁 |
| 文件大?。?/td> | 597K |
| 代理商： | TSB43AA82A1 |
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2.7
Packet Distributor
The packet distributor module provides the packet routing service for each FIFO module. In SBP-2 mode, all request
and response packets are properly routed to the correct FIFO, and sent to corresponding initiators. In direct print
protocol (DPP) mode, the packet distributor filters a request packet by its address and then saves it into the correct
receive FIFO.
2.8
Packetizer
The packetizer module provides packetization for a transmit packet. The data stream from the DMA FIFO is split into
small packets that meet the SBP-2 requirements. A read or write request header is attached to each packet with a
correctly incremented destination address. The transaction/timer manager provides busy retry and split transaction
timer control if required. The packetizer also provides auto-page table fetch service. The internal auto-fetch module
sends a read request to the present page address, and the DMA automatically sends data to the requested address
set by the Page Table Element. At the end of packetizer, if the DMA function has successfully completed, the DMA
automatically sends a status block packet.
2.9
Configuration ROM
The ConfigROM provides the configuration ROM required by the IEEE 1212 standard
2
. The ConfigROM module
supports the auto response service for a ConfigROM read request and records the transaction history. The host
controller can load ConfigROM data during node initialization. Once initialized, the ConfigROM is accessible by peer
node read requests. See Section 5 for more details.
2.10 Link Core
The link core provides link layer service such as correctly formatted IEEE 1394-1995
3
and IEEE 1394a-2000
4
asynchronous transmit and receive packets. It also generates and inspects the 32-bit cyclic redundancy check
(CRC). This link core does not support isochronous service.
2.11 PHY (and PHY Interface)
The TSB43AA82A has an integrated 400-Mbps two-port physical layer. The PHYsical (PHY) interface provides
PHY-level service to the link layer service. See Section 11 for more details.
2.12 FIFOs
The TSB43AA82A has three FIFO types, asynchronous command FIFOs, configuration ROM FIFOs and DMA
FIFOs. These FIFO types have maximum sizes of 378 quadlets, 126 quadlets, and 1182 quadlets respectively.
Except for the MTQ and MRF, the FIFO sizes are adjustable. The sum of all the FIFOs in a type must not exceed the
maximum size. See Section 4 for more information on the asynchronous command FIFOs, Section 5 for more
information on ConfigROM/LOG FIFOs, and Section 8 for more information on BDFIFOs.
2 IEEE Std 1212-1991,
IEEE Standard Control and Status Register (CSR) Architecture for Microcomputer Buses
3 IEEE Std 1394-1995,
IEEE Standard for a High Performance Serial Bus
4 IEEE Std 1394a-2000,
IEEE Standard for a High Performance Serial Bus - Amendment 1
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TSB43AA82AI | 制造商:TI 制造商全稱:Texas Instruments 功能描述:1394 Integrated PHY and Link-Layer Controller for SBP-2 Products and DPP Products |
| TSB43AA82AIPGE | 功能描述:1394 接口集成電路 Hi Perf Integr Phy & Link Layer Chip RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB43AA82AIPGEEP | 功能描述:1394 接口集成電路 Mil Enh Int PHY and Link-Layer Cntrlr RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB43AA82APGE | 功能描述:1394 接口集成電路 Hi Perf Integr Phy & Link Layer Chip RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB43AA82APGEG4 | 功能描述:1394 接口集成電路 Hi Perf Integr Phy & Link Layer Chip RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
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