參數(shù)資料
型號： TSB43AA82A1
廠商： Texas Instruments, Inc.
英文描述： 1394 integrated PHY and link layer controller(1394集成PHY和鏈路層控制器)
中文描述： 1394綜合物理層和鏈路層控制器（1394集成物理層和鏈路層控制器）
文件頁數(shù)： 75/146頁
文件大小： 597K
代理商： TSB43AA82A1
49
Table 4-8. Generic Receive Format Descriptions (Continued)
FIELD NAME
quadlet data
DESCRIPTION
For write requests and read responses, this field holds the transferred data. For write responses and read requests, this field
is not present.
For write requests, read responses, and locks, this field indicates the number of bytes being transferred. For read requests,
this field indicates the number of bytes of data to be read. A write-response packet does not use this field.
Note: The number of bytes does not include the header, only the bytes of block data.
data_length
extended_tCode
The block extended_tCode to be performed on the data in this packet. See Table 6-10 of the IEEE 1394-1995 standard.
block data
For write requests and read responses, this field holds the transferred data. For write responses and read requests, this field
is not present.
4.5
Management and Command FIFOs (MTQ/CTQ and MRF/CRF)
MTQ/CTQ
transmit refers to the use of the MTQ/CTQ interface.
Packet transmission with MTQ/CTQ appears with
the format shown in Section 4.5.1. As with other packet transmissions, it is accessed through the CFR (70h-78h).
The tLabel and the tCode attached to a packet direct each request and response packet to the appropriate FIFO. A
response packet needs to have the same tLabel as its request packet. With this rule, TSB43AA82A assigns the
response packet from the initiator to each receive FIFO.
4.5.1
MTQ/CTQ Format
Packets transmitted from the MTQ/CTQ are in the same format as a read request block transmit to the ATF. However,
as stated in Section 4.2.1, this must be a block read request with the specified tLabel. The block-transmit format is
shown in Figure 411 and field descriptions are shown in Table 49. The first quadlet contains packet control
information. The second and third quadlets contain the 64-bit, quadlet-aligned address. The data_length of a packet
transmitted from MTQ should be set to 32 bytes.
10 11
12 13
14 15
0
1
2
3
4
5
6
7
8
9
16 17
18 19
20 21
22 23
24 25
26 27
28 29
30 31
Reserved
spd
tLabel
rt
tCode
prior
destination ID
destination_offset_high
destination_offset_low
data_length
extended_tCode
21 22 23
0
1
2
3
4
5
6
Figure 411. MTQ/CTQ Transmission Block Read Packet Format
7
8
9
10 11 12
13 14
15 16 17
18 19 20
24 25 26
27 28 29
30 31
Table 49. Block-Transmit Format Descriptions
FIELD NAME
DESCRIPTION
spd
This field indicates the speed at which this packet is to be sent. 00 = 100 Mbps, 01 = 200 Mbps, and 10 = 400 Mbps,
and 11 is undefined for this implementation.
tLabel
This field is the transaction label, which is a unique tag for each outstanding transaction between two nodes. This is
used to pair up a response packet with its corresponding request packet. When using the MTQ, tLabel must be set to
10_xxxx. When using the CTQ, tLabel must be set to 11_xxxx.
rt
The retry code for this packet is 00 = new, 01 = retry_X, 10 = retryA, and 11 = retryB.
tCode
tCode is the transaction code for this packet (see Table 6-9 of IEEE 1394-1995 standard).
prior
The priority level for this packet. For cable implementation, the value of the bits must be zero. For backplane
implementation, see clause 5.4.1.3 and 5.4.2.1 of the IEEE 1394-1995 standard.
destination ID
This is the concatenation of the 10-bit bus number and the 6-bit node number that forms the node address to which
this packet is being sent.
destination_offset_high,
destination_offset_low
The concatenation of these two fields addresses a quadlet in the destination node address space. This address must
be quadlet aligned (modulo 4). The upper four bits of the destination_offset_high field are used as the response code
for lock-response packets and the remaining bits are reserved.
data_length
The number of bytes of data to be transmitted in the packet. The data_length of packet transmitted from MTQ must be
set to 32 bytes.
extended_tCode
The block extended_tCode to be performed on the data in this packet. See Table 6-10 of the IEEE 1394-1995
standard.
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TSB43AA82AIPGE 功能描述:1394 接口集成電路 Hi Perf Integr Phy & Link Layer Chip RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray
TSB43AA82AIPGEEP 功能描述:1394 接口集成電路 Mil Enh Int PHY and Link-Layer Cntrlr RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray
TSB43AA82APGE 功能描述:1394 接口集成電路 Hi Perf Integr Phy & Link Layer Chip RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray
TSB43AA82APGEG4 功能描述:1394 接口集成電路 Hi Perf Integr Phy & Link Layer Chip RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray
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