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參數(shù)資料
| 型號(hào)： | TSC2100IRHBRG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQCC32 |
| 封裝： | 5 X 5 MM, GREEN, PLASTIC, QFN-32 |
| 文件頁(yè)數(shù)： | 77/77頁(yè) |
| 文件大?。?/td> | 1079K |
| 代理商： | TSC2100IRHBRG4 |
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TSC2100
SLAS378 NOVEMBER 2003
www.ti.com
9
AUDIO INTERFACE TIMING DIAGRAMS
LRCK/ADWS
BCLK
DOUT
DIN
td (WS)
td (DOWS)
td (DOBCLK)
ts (DI)
th (DI)
Figure 1. I2S/LJF/RJF Timing in Master Mode
TYPICAL TIMING REQUIREMENTS (FIGURE 1)
All specifications at 25°C, DVDD = 1.8 V (1)
PARAMETER
IOVDD = 1.1 V IOVDD = 3.3 V
UNITS
PARAMETER
MIN
MAX
MIN
MAX
UNITS
td (WS)
ADWS/LRCK delay
25
15
ns
td (DOWS)
ADWS to DOUT delay (for LJF mode)
25
15
ns
td (DOBCLK)
BCLK to DOUT delay
25
15
ns
ts(DI)
DIN setup
6
ns
th(DI)
DIN hold
6
ns
tr
Rise time
10
6
ns
tf
Fall time
10
6
ns
(1) These parameters are based on characterization and are not tested in production.
LRCK/ADWS
BCLK
DOUT
DIN
td (WS)
td (DOBCLK)
ts (DI)
th (DI)
td (WS)
Figure 2. DSP Timing in Master Mode
TYPICAL TIMING REQUIREMENTS (FIGURE 2)
All specifications at 25°C, DVDD = 1.8 V(1)
PARAMETER
IOVDD = 1.1 V IOVDD = 3.3 V
UNITS
PARAMETER
MIN
MAX
MIN
MAX
UNITS
td (WS)
ADWS/LRCK delay
25
15
ns
td (DOBCLK)
BCLK to DOUT delay
25
15
ns
ts(DI)
DIN setup
6
ns
th(DI)
DIN hold
6
ns
tr
Rise time
10
6
ns
tf
Fall time
10
6
ns
(1) These parameters are based on characterization and are not tested in production.
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