參數(shù)資料
型號(hào): TSC21020F-20MBP833
英文描述: IC CYCLONE III FPGA 25K 144-EQFP
中文描述: 數(shù)字信號(hào)處理器| 32位|的CMOS | RAD數(shù)據(jù)通信硬| QFL | 256PIN |陶瓷
文件頁(yè)數(shù): 19/51頁(yè)
文件大?。?/td> 763K
代理商: TSC21020F-20MBP833
19
TSC21020F
4153F
AERO
06/03
|
PM < addr24 >
|
14b.
ureg =
|
DM < addr32 >
|
;
|
PM < addr24 >
|
= ureg ;
15a.
|
DM (< data32 >, Ia)
|
|
PM (< data24 >, Ic)
|
ureg =
15b.
|
DM < data32 >, Ia
|
;
|
PM < data24 >, Ic
|
16.
|
DM(Ia,Mb)
|
= < data32 >;
|
PM(Ic,Md)
|
ureg = < data32 >;
17.
Miscellaneous Instructions
18.
BIT
|
SET
|
|
CLR
|
|
TGL
|
|
TST
|
|
XOR
|
|
(Ia, < data32 >
|
Ic < data32 >
sreg < data32 > :
19a.
MODIFY
| ;
|
19b.
BITREV
(Ia, < data32 >) ;
20.
|
PUSH
|
|
POP
|
NOP;
IDLE;
LOOP,
|
PUSH
|
|
POP
|
STS ;
21.
22.
Table 3.
Syntax Notation Conventions
Notation
Meaning
UPPERCASE
Explicit syntax - assembler keyword (notation only; assembler is not case-
sensitive and lowercase is the preferred programming convention)
;
Instruction terminator
,
Separates parallel operations in an instruction
italics
|
between lines
|
List of options (choose one)
Optional part of instruction
<datan>
n-bit immediate data value
<addrn>
n-bit immediate address value
<reladdrn>
n-bit immediate PC-relative address value
compute
ALU, multiplier, shifter or multifunction operation (from Tables 4-7)
shiftimm
Shifter immediate operation (from Table 6)
condition
Status condition (from Table 2)
termination
Termination condition (from Table 2)
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