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| 型號： | TSC2111IRGZTG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 音頻／視頻放大 |
| 英文描述： | 0.4 W, 1 CHANNEL, AUDIO AMPLIFIER, QCC48 |
| 封裝： | PLASTIC, QFN-48 |
| 文件頁數(shù)： | 42/99頁 |
| 文件大小： | 1143K |
| 代理商： | TSC2111IRGZTG4 |
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TSC2111
SLAS495A JUNE 2006 REVISED OCTOBER 2007
www.ti.com
47
converted data is going to be written. The trigger pointer indicates the location at which an interrupt will be
generated if the write pointer reaches that location. Trigger level is the number of the data points needed to be
present in the FIFO before generating an interrupt. For e.g., XY continuous scan mode with trigger level set
to 8, the TSC2111 generates interrupt after writing (X1, Y1), (X2, Y2), (X3, Y3), (X4, Y4) i.e. 4 data-pairs or 8
data. Figure 35 shows the case when trigger level is programmed as 32. On resetting buffer mode, RDPTR
moves to location 1, WRPTR moves to location 1, and TGPTR moves to location equal to programmed trigger
level.
The user can select the input or input sequence, which needs to be converted, from the ADCSM bits of control
register 00H/page 1. The converted values are written in a predefined sequence to the circular buffer. The user
has flexibility to program a specific trigger level in order to choose the configuration which best fits the
application. When the number of converted data, written in FIFO, becomes equal to the programmed trigger
level then the device generates an interrupt signal on /PINTDAV pin. In buffer mode, the user should program
this pin as Data Available (DATA_AVA). In buffer mode, touch screen related conversions (X, Y, Z1, Z2) are
allowed only in self-controlled mode and nontouch screen related conversions (BAT, AUX1, AUX2, TEMP1,
TEMP2) are allowed only in host-controlled mode.
Buffer mode can be used in single-shot conversion or continuous conversion mode.
In single shot conversion mode, once the number of data written reaches programmed trigger level, the
TSC2111 generates an interrupt and waits for the user to start reading. As soon as the user starts reading the
first data from the last converted set, the TSC2111 clears the interrupt and starts a new set of conversions and
the trigger pointer is incremented by the programmed trigger level. An interrupt is generated again when the
trigger condition is satisfied.
In continuous conversion mode, once number of data written reaches the programmed trigger level, the
TSC2111 generates an interrupt. It immediately starts a new set of conversions and the trigger pointer is
incremented by the programmed trigger level. An interrupt gets cleared either by writing the next converted data
into the FIFO or by starting to read from the FIFO.
See the section Conversion Time Calculation for the TSC2111 and subsection Buffer Mode Operation in this
data sheet for timing diagrams and conversion time calculations.
Depending upon how the user is reading data, the FIFO can become empty or full. If the user is trying to read
data even if the FIFO is empty, then RDPTR keeps pointing to same location. If the FIFO gets full then the next
location is overwritten with newly converted data and the read pointer is incremented by one.
While reading the FIFO, the TSC2111 provides FIFO empty and full status flags along with the data. The user
can also read a status flag from control register 02H/page 1.
DIGITAL INTERFACE
RESET
The device requires reset after power up. This requires a low-to-high transition on the RESET pin after power
up for correct operation. Reset initializes all the internal registers, counters and logic.
Hardware Power-Down
Hardware power-down powers down all the internal circuitry to save power. All the register contents are
maintained. Putting the TSC2111 into hardware power-down circuit also disables the pen-touch detect circuit.
General Purpose I/O
The TSC2111 has two general purpose I/O (GPIO1 and GPIO2), which can be programmed either as inputs
or outputs. As outputs they can be programmed to control external logic through the TSC2111 registers or send
interrupts to the host processor on events like button detect, headset insertion, headset removal,
Auxiliary/temperature outside threshold range etc. As inputs they can be used by the host-processor to monitor
logic states of signals on the system through the TSC2111 registers.
SPI Digital Interface
All TSC2111 control registers are programmed through a standard SPI bus. The SPI allows full-duplex,
synchronous, serial communication between a host processor (the master) and peripheral devices (slaves).
The SPI master generates the synchronizing clock and initiates transmissions. The SPI slave devices depend
on a master to start and synchronize transmissions.
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