參數(shù)資料
型號: TSC87251G2D-L16CER
廠商: Atmel
文件頁數(shù): 38/77頁
文件大小: 0K
描述: IC MCU 8BIT 32K OTP 16MHZ 44VQFP
標準包裝: 1,500
系列: 8x251
核心處理器: C251
芯體尺寸: 8/16-位
速度: 16MHz
連通性: EBI/EMI,I²C,Microwire,SPI,UART/USART
外圍設(shè)備: POR,PWM,WDT
輸入/輸出數(shù): 32
程序存儲器容量: 32KB(32K x 8)
程序存儲器類型: OTP
RAM 容量: 1K x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 5.5 V
振蕩器型: 內(nèi)部
工作溫度: 0°C ~ 70°C
封裝/外殼: 44-LQFP
包裝: 帶卷 (TR)
其它名稱: TSC87251G2DL16CER
43
AT/TSC8x251G2D
4135F–8051–11/06
PSEN# and the other control signals have to be released to complete a sequence of
programming operations or a sequence of programming and verifying operations.
Figure 6.
Setup for Programming
Table 36.
Programming Modes
Notes: 1. Signature Bytes are not user-programmable.
2. The ALE/PROG# pulse waveform is shown in Figure 23 page 59.
Verify Algorithm
Figure 7 shows the hardware setup needed to verify the TSC87251G2D
EPROM/OTPROM or TSC83251G2D ROM areas:
The chip has to be put under reset and maintained in this state until the completion
of the verifying sequence.
PSEN# and the other control signals (ALE and Port 0) have to be set to a high level.
Then PSEN# has to be to forced to a low level after two clock cycles or more and it
has to be maintained in this state until the completion of the verifying sequence (see
below).
The voltage on the EA# pin must be set to VDD and ALE must be set to a high level.
The Verifying Mode is selected according to the code applied on Port 0. It has to be
applied until the completion of this verifying operation.
The verifying address is applied on Ports 1 and 3 which are respectively the MSB
and the LSB of the address.
ROM Area
(1)
RST
EA#/VPP
PSEN
#
ALE/PROG#
(2)
P0
P2
P1(MSB) P3(LSB)
On-chip Code
Memory
1VPP
0
1 Pulse
68h
Data
16-bit Address
0000h-7FFFh (32
kilobytes)
Configuration
Bytes
1VPP
0
1 Pulse
69h
Data
CONFIG0: FFF8h
CONFIG1: FFF9h
Lock Bits
1
VPP
0
1 Pulse
6Bh
X
LB0: 0001h
LB1: 0002h
LB2: 0003h
Encryption Array
1
VPP
0
1 Pulse
6Ch
Data 0000h-007Fh
VDD
PSEN#
ALE/PROG#
EA#/VPP
XTAL1
VDD
4 to 12 MHz
RST
VPP
100 ms pulses
VSS/VSS1/VSS2
Mode
VDD
A[7:0]
A[14:8]
Data
P0[7:0]
P3[7:0]
P1[7:0]
P2[7:0]
TSC87251G2D
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