參數(shù)資料
型號(hào)： TSPC106AVGSU83CG
英文描述： MEMORY CONTROLLER
中文描述： 內(nèi)存控制器
文件頁(yè)數(shù)： 3/40頁(yè)
文件大?。?/td> 569K
代理商： TSPC106AVGSU83CG
3
TSPC106
2102B
–
HIREL
–
02/02
The TSPC106 provides support for the following configurations of 60x processors and
L2 cache:
Up to four 60x processors with no L2 cache
A single 60x processor plus a direct-mapped, lookaside L2 cache using the internal
L2 cache controller of the TSPC106
Up to four 60x processors plus an externally controlled L2 cache (e.g., the Motorola
MPC2604GA integrated L2 lookaside cache)
The memory interface controls processor and PCI interactions to main memory and is
capable of supporting a variety of configurations using DRAM, EDO, or SDRAM and
ROM or Flash ROM.
The PCI interface of the TSPC106 complies with the PCI local bus specification Revi-
sion 2.1 and follows the guidelines in the PCI System Design Guide Revision 1.0 for
host bridge architecture. The PCI interface connects the processor and memory buses
to the PCI bus to which I/O components are connected. The PCI bus uses a 32-bit mul-
tiplexed address/data bus plus various control and error signals.
The PCI interface of the TSPC106 functions as both a master and target device. As a
master, the 106 supports read and write operations to the PCI memory space, the PCI
I/O space and the PCI configuration space. The TSPC106 also supports PCI special-
cycle and interrupt-acknowledge commands. As a target, the TSPC106 supports read
and write operations to system memory.
The TSPC106 provides hardware support for four levels of power reduction: doze, nap,
sleep and suspend. The design of the TSPC106 is fully static, allowing internal logic
states to be preserved during all power saving modes.
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