參數(shù)資料
型號： TSPC106AVGU83CG
英文描述： MEMORY CONTROLLER
中文描述： 內(nèi)存控制器
文件頁數(shù)： 11/40頁
文件大?。?/td> 569K
代理商： TSPC106AVGU83CG
11
TSPC106
2102B
–
HIREL
–
02/02
DH[0:31],
DL[0:31]
Data bus
64
The data bus is comprised of two halves - data bus high (DH[0:31])
and data bus low (DL[0:31]). The data bus has the following byte lane
assignments:
O
Represents the value of data being driven by the TSPC106.
I
Represents the state of data being driven by a 60x processor, the local
bus slave, the L2 cache or the memory subsystem.
GBL
Global
1
I/O
Indicates that an access is global and hardware needs to enforce
coherency.
LBCLAIM
Local bus slave
cycle claim
1
I
Indicates that the local bus slave claims the transaction and is
responsible for driving TA during the data tenure.
MCP
Machine check
1
O
Indicates that the TSPC106 detected a catastrophic error and the 60x
processor should initiate a machine check exception.
TA
Transfer
acknowledge
1
O
Indicates that the data has been latched for a write operation or that
the data is valid for a read operation, thus terminating the current data
beat. If it is the last (or only) data beat, this also terminates the data
tenure.
I
Indicates that the external L2 cache or local bus slave has latched data
for a write operation or is indicating the data is valid for a read
operation. If it is the last (or only) data beat, then the data tenure is
terminated.
TBST
Transfer burst
1
O
Indicates that a burst transfer is in progress.
I
Indicates that a burst transfer is in progress.
TEA
Transfer error
acknowledge
1
O
Indicates that a bus error has occurred. Assertion of TEA terminates
the transaction in progress. An unsupported memory transaction, such
as a direct-store access or a graphics read or write, causes the
assertion of TEA (provided TEA is enabled).
TS
Transfer start
1
O
Indicates that the TSPC106 has started a bus transaction and that the
address and transfer attribute signals are valid. Note that the
TSPC106 only initiates a transaction to broadcast the address of a PCI
access to memory for snooping purposes.
I
Indicates that a 60x bus master has begun a transaction and that the
address and transfer attribute signals are valid.
Table 2.
60x Processor Interface Signals (Continued)
Signal
Signal Name
Number of
Pins
I/O
Signal Description
Data Byte
Byte Lane
DH[0:7]
0
DH[8:15]
1
DH[16:23]
2
DH[24:31]
3
DL[0:7]
4
DL[8:15]
5
DL[16:23]
6
DL[24:31]
7
相關(guān)PDF資料
PDF描述
TSPC106AMG66CE MEMORY CONTROLLER
TSPC106AMG66CG MEMORY CONTROLLER
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TSPC106AMG83CG MEMORY CONTROLLER
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