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| 型號： | TSPC106AVGU83CG |
| 英文描述： | MEMORY CONTROLLER |
| 中文描述： | 內(nèi)存控制器 |
| 文件頁數(shù)： | 14/40頁 |
| 文件大?。?/td> | 569K |
| 代理商： | TSPC106AVGU83CG |
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14
TSPC106
2102B
–
HIREL
–
02/02
Multiple Processor
Signals
When a system implementation uses more than one 60x processor, nine of the internal
L2 cache controller signals change their functions.
Note that in a multi-processor system, with the exception of the bus grant, bus request
and data bus grant signals, all of the 60x processor interface signals are shared by all
60x processors.
Table 5.
Multiple Processor Signals
Signal
Signal Name
Numberof
Pins
I/O
Signal Description
BG1
DIRTY_OUT
Bus grant 1
1
O
Indicates that processor 1 may, with the proper qualification, begin a
60x bus transaction and assume mastership of the address bus.
BG2
TWE
Bus grant 2
1
O
Indicates that processor 2 may, with the proper qualification, begin a
60x bus transaction and assume mastership of the address bus.
BG3
DCS
Bus grant 3
1
O
Indicates that processor 3 may, with the proper qualification, begin a
60x bus transaction and assume mastership of the address bus.
BR1
DIRTY_IN
Bus request 1
1
I
Indicates that processor 1 requires mastership of the 60x bus for a
transaction.
BR2
TV
Bus request 2
1
I
Indicates that processor 2 requires mastership of the 60x bus for a
transaction.
BR3
BA0
Bus request 3
1
I
Indicates that processor 3 requires mastership of the 60x bus for a
transaction.
DBG1
TOE
Data bus grant 1
1
O
Indicates that processor 1 may, with the proper qualification, assume
mastership of the 60x data bus.
DBG2
DWE0
Data bus grant 2
1
O
Indicates that processor 2 may, with the proper qualification, assume
mastership of the 60x data bus.
DBG3
DWE1
Data bus grant 3
1
O
Indicates that processor 3 may, with the proper qualification, assume
mastership of the 60x data bus.
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