參數(shù)資料
型號(hào)： TSPC106AVGU83CG
英文描述： MEMORY CONTROLLER
中文描述： 內(nèi)存控制器
文件頁(yè)數(shù)： 31/40頁(yè)
文件大?。?/td> 569K
代理商： TSPC106AVGU83CG
31
TSPC106
2102B
–
HIREL
–
02/02
Figure 14.
Test Access Port Timing Diagram
Architectural
Overview
60x Processor Interface
The TSPC106 supports a programmable interface to a variety of PowerPC microproces-
sors operating at select bus speeds.The address bus is 32 bits wide and the data bus is
64 bits wide. The 60x processor interface of the TSPC106 uses a subset of the 60x bus
protocol, supporting single-beat and burst data transfers. The address and data buses
are decoupled to support pipelined transactions.
Two signals on the TSPC106, local bus slave claim (LBCLAIM) and data bus grant local
bus slave (DBGLB), are provided for an optional local bus slave. However, the local bus
slave must be capable of generating the transfer acknowledge (TA) signal to interact
with the 60x processor(s).
Depending on the system implementation, the processor bus may operate at the PCI
bus clock rate or at two or three times the PCI bus clock rate. The 60x processor bus is
synchronous with all timing relative to the rising edge of the 60x bus clock.
Secondary (L2)
Cache/Multiple
Processor Interface
The 106 provides support for the following configurations of 60x processors and L2
cache:
Up to four 60x processors with no L2 cache
A single 60x processor plus a direct-mapped, lookaside, L2 cache using the internal
L2 cache controller of the TSPC106
Up to four 60x processors plus an externally-controlled L2 cache
The internal L2 cache controller generates the arbitration and support signals necessary
to maintain a write-through or write-back L2 cache. The internal L2 cache controller sup-
ports either asynchronous SRAMs, pipelined burst SRAMs or synchronous burst
SRAMs, using byte parity for data error detection.
TCK
12
12
13
Input Data Valid
Output Data Valid
Output Data Valid
10
11
TDI, TMS
TDO
TDO
TDO
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