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參數(shù)資料
| 型號： | TSS901ESASL3 |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 3 CHANNEL(S), 200M bps, SERIAL COMM CONTROLLER, QFP196 |
| 封裝： | MQFP-196 |
| 文件頁數(shù)： | 26/28頁 |
| 文件大?。?/td> | 601K |
| 代理商： | TSS901ESASL3 |
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7
Rev. B - July 29, 1999
TSS901E
2. Register Set
This chapter describes the TSS901E registers which can be read or written by the HOCI or via the link (in case
the "control by link" is enabled) to control TSS901E operations. All TSS901E control operations are performed
by writes or reads of the respective registers. Most of the control operations are obvious from the content of the
registers.
General Conventions:
bit 0 (D0) = least significant bit,
bit 7 (D7) = most significant bit (or bit 15 resp. bit 31)
D x:0 means data bit x until bit 0.
2.1 Access by HOCI: HOCI data transfer
Big/Little endian selection of the HOCI is done using a special pin (HOSTBIGE) of the TSS901E. By connecting
this pin to either Vcc or GND the HOCI is configured to be in little or big endian mode as follows:
When Signal HOSTBIGE = '0' (GND), the HOCI data port is in little endian mode.
When Signal HOSTBIGE = '1' (Vcc), the HOCI data port is in big endian mode.
Little endian mode selected:
8 bit data port (default after reset)
-
register byte 0 is connected with pin HDATA0 - HDATA7
16 bit data port
-
register byte 0 is connected with pin HDATA0 - HDATA7
-
register byte 1 is connected with pin HDATA8 - HDATA15
32 bit data port
-
register byte 0 is connected with pin HDATA0 - HDATA7
-
register byte 1 is connected with pin HDATA8 - HDATA15
-
register byte 2 is connected with pin HDATA16 - HDATA23
-
register byte 3 is connected with pin HDATA24 - HDATA31
Big endian mode selected:
8 bit data port (default after reset)
-
register byte 0 is connected with pin HDATA24 - HDATA31
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