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參數(shù)資料
| 型號： | TSS901ESASL3 |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 3 CHANNEL(S), 200M bps, SERIAL COMM CONTROLLER, QFP196 |
| 封裝： | MQFP-196 |
| 文件頁數(shù)： | 5/28頁 |
| 文件大小： | 601K |
| 代理商： | TSS901ESASL3 |
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13
Rev. B - July 29, 1999
TSS901E
Signal Name
Type
Function
max. output
current [mA]
load [pF]
CMRD*
O/Z
Communication memory read strobe. This pin is asserted when the
TSS901E reads data from memory.
825
CMWR*
O/Z
Communication memory write strobe. This pin is asserted when
the TSS901E writes to data memory.
825
CMADR(15:0)
O/Z
Communication memory address. The TSS901E outputs an address
on these pins.
825
CMDATA(31:0)
IOZ
Communication memory data. The TSS901E inputs and outputs
data from and to com. memory on these pins.
350
COCI
I
Communication interface 'occupied' input signal
3
50
COCO
O/Z
Communication interface 'occupied' output signal
CAM
I
Communication interface arbitration master input signal
1: master
0: slave
CPUR*
O/Z
CPU Reset Signal
3
50
SES(3:0)*
O/Z
Specific External Signals
3
50
LDI1
I
Link Data Input channel 1
LSI1
I
Link Strobe Input channel 1
LDO1
O/Z
Link Data Output channel 1
12
25
LSO1
O/Z
Link Strobe Output channel 1
12
25
LEN1
O/Z
Link Enable Out (for external drivers)
3
50
LDI2
I
Link Data Input channel 2
LSI2
I
Link Strobe Input channel 2
LDO2
O/Z
Link Data Output channel 2
12
25
LSO2
O/Z
Link Strobe Output channel 2
12
25
LEN2
O/Z
Link Enable Out (for external drivers)
3
50
LDI3
I
Link Data Input channel 3
LSI3
I
Link Strobe Input channel 3
LDO3
O/Z
Link Data Output channel 3
12
25
LSO3
O/Z
Link Strobe Output channel 3
25
LEN3
O/Z
Link Enable Out (for external drivers)
3
50
TRST*
I
Test Reset. Resets the test state machine.
TCK
I
Test Clock. Provides an asynchronous clock for JTAG boundary
scan.
TMS
I
Test Mode Select. Used to control the test state machine.
TDI
I
Test Data Input. Provides serial data for the boundary scan logic.
TDO
O/Z
Test Data Output. Serial scan output of the boundary scan path.
3
50
RESET*
I
TSS901E Reset. Sets the TSS901E to a known state. This input
must be asserted (low) at power-up. The minimum width of RESET
low is 5 cycles of CLK10 in parallel with CLK running.
CLK
I
External clock input to TSS901E (max. 25 Mhz).
Must be derived from RAM access time.
CLK10
I
External clock input to TSS901E DS-links (application specific,
nominal 10 Mhz). Used to generate to transmission speed and link
disconnect timeout.
PLLOUT
O
Output of internal PLL. Used to connect a network of external RC
devices.
VCC
Power Supply
GND
Ground
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