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參數(shù)資料
| 型號： | TSS901ESASL3 |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 3 CHANNEL(S), 200M bps, SERIAL COMM CONTROLLER, QFP196 |
| 封裝： | MQFP-196 |
| 文件頁數(shù)： | 28/28頁 |
| 文件大?。?/td> | 601K |
| 代理商： | TSS901ESASL3 |
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9
Rev. B - July 29, 1999
TSS901E
2.2.1 TSS901E status and control registers
2.2.2 TSS901E channel 1 status and control registers
Port Width /
Address (hex)
Register
Function
Reset Value
(hex)
Access
32
16
8
00
SICR
TSS901E Interface Control Register
00
r / w
01
TRS_CTRL
Transmit-Speed-Base Register
0A
r / w
02
ROUTE_CTRL
Routing Enable / Status Register
00
r
03
reserved
00
04
06
04
05
06
07
ISR
Interrupt Status Register
04010040
ro
08
0A
08
09
0A
0B
IMR
Interrupt Mask Register
00000000
r / w
0C
COMI_CS0R
COMI Chip Select 0 upper address boundary Register
FF
r / w
0D
reserved
00
0E
COMI_ACR
COMI Arbitration Control Register
08
r / w
0F
PRCIR
PRCI Register
00
r / w
Port Width /
Address (hex)
Register
Function
Reset Value
(hex)
Access
32
16
8
10
CH1_DSM_MODR
channel 1 DSM mode Register
03
r / w
11
CH1_DSM_CMDR
channel 1 DSM command Register
00
r / w
12
CH1_DSM_STAR
channel 1 DSM status Register
00
r / w
13
CH1_DSM_TSTR
channel 1 DSM test Register
00
r / w
14
CH1_ADDR
channel 1 address Register
00
r / w
15
CH1_RT_ADDR
channel 1 Route Address Register
00
r / w
16
CH1_PR_STAR
channel 1 Protocol Status Register
04
r / w
17
reserved
00
---
18
CH1_CNTRL1
channel 1 control Register 1
00
r / w
19
CH1_CNTRL2
channel 1 control Register 2
00
r / w
1A
CH1_HTID
channel 1 Header Transaction ID byte
00
ro
1B
CH1_HCNTRL
channel 1 Header control byte
00
ro
1C
CH1_ESR1
channel 1 detailed error source register 1
00
r / w
1D
CH1_ESR2
channel 1 detailed error source register 2
00
r / w
1E
reserved
00
---
1F
CH1_COMICFG
channel 1 COMI configuration register
00
r / w
20
21
CH1_TX_SAR
channel 1 transmit Start Address Register
0000
r / w
22
23
CH1_TX_EAR
channel 1 transmit End Address Register
0000
r / w
24
25
CH1_TX_CAR
channel 1 transmit Current Address Register
0000
ro
26
CH1_TX_FIFO
channel 1 transmit FIFO
--
wo
27
CH1_TX_EOPB
channel 1 transmit EOP Bit Register
--
wo
28
29
CH1_RX_SAR
channel 1 receive Start Address Register
0000
r / w
2A
2B
CH1_RX_EAR
channel 1 receive End Address Register
0000
r / w
2C
2D
CH1_RX_CAR
channel 1 receive Current Address Register
0000
ro
2E
CH1_RX_FIFO
channel 1 receive FIFO
xxxxxxxx
ro
2F
CH1_STAR
channel 1 Status Register
01
ro
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TSS902EMA | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:VITERBI DECODER|CMOS|QFL|132PIN|CERAMIC |
| TSS902EMA/883 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:VITERBI DECODER|CMOS|QFL|132PIN|CERAMIC |
| TSS902EMA-E | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:VITERBI DECODER|CMOS|QFL|132PIN|CERAMIC |
| TSS902EMAP883 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:VITERBI DECODER|CMOS|QFL|132PIN|CERAMIC |
| TSS902EMAPIND | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:VITERBI DECODER|CMOS|QFL|132PIN|CERAMIC |
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