參數(shù)資料
型號(hào)： TVP3703-135
廠商： Texas Instruments, Inc.
英文描述： Video Interface PALETTE Exract(雙PLL，先進(jìn)的視頻接口調(diào)色器)
中文描述： 視頻接口調(diào)色板Exract（雙鎖相環(huán)，先進(jìn)的視頻接口調(diào)色器）
文件頁(yè)數(shù)： 15/21頁(yè)
文件大?。?/td> 427K
代理商： TVP3703-135
TVP3703
VIDEO INTERFACE PALETTE
TRUE-COLOR CMOS RAMDAC
SLAS100 – MARCH 1996
15
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
timing requirements
micro port
PARAMETER
TVP3703-170
TVP3703-135
UNIT
MIN
50
MAX
MIN
75
MAX
tw(WLWH)
tw(RLRH)
trec(WHWL)
trec(RHRL)
tsu(SVL)
th(LSX)
tsu(DVWH)
th(WHDX)
NOTES:
Pulse duration, WR low
ns
Pulse duration, RD low
50
50
ns
Recovery time preceding a write (see Notes 6 and 7)
3
×
tc(CHCH)
6
×
tc(CHCH)
10
3
×
tc(CHCH)
6
×
tc(CHCH)
10
ns
Recovery time preceding a read (see Notes 6 and 7)
ns
Setup time, RS0-RS2
ns
Hold time, RS0-RS2
4
4
ns
Setup time, write data
10
10
ns
Hold time, write data
10
10
ns
6. tc(CHCH) (PCLK period) is specified in the pixel port timing requirements table.
7. Access recovery times are specified as the time before a particular access because the worst case access (reading a red palette
color value) can occur after either reading a blue palette color value or after writing to the address register (read mode).
PLL frequency select
PARAMETER
TVP3703-170
TVP3703-135
UNIT
MIN
50
MAX
MIN
50
MAX
tw(SHSL)
tw(SLSH)
tsu(SVSL)
th(SLSX)
NOTE 8: The VS0–VS3 latches are transparent when STROBE is at logic 1.
Pulse duration, STROBE high
ns
Pulse duration, STROBE low
50
50
ns
Setup time, VS0–VS3 (see Note 8)
20
30
ns
Hold time, VS0–VS3 (see Note 8)
20
30
ns
pixel port
PARAMETER
TVP3703-170
MIN
11.7
TVP3703-135
MIN
14.8
UNIT
MAX
MAX
PCLK cycle time (pixel mode 05h – double 8-bit, indexed)
ns
tc(CHCH)
PCLK cycle time (pixel mode 09h – double 24-bit, direct)
9.08
9.08
ns
PCLK cycle time (all other pixel modes)
9.08
9.08
ns
tw(CLCH)
tw(CHCL)
tsu(PVCH)
th(CHPX)
NOTE 9: The pixel address input to the color palette should be set up as a valid logic level with the appropriate setup and hold times to each rising
edge of PCLK (this requirement must also be met during the blanking period).
Pulse duration, PCLK low
2.9
4
ns
Pulse duration, PCLK high
2.9
3
ns
Setup time, pixel data (see Note 9)
2
2
ns
Hold time, pixel data (see Note 9)
2
2
ns
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相關(guān)代理商/技術(shù)參數(shù)
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TVP3703-135CFN 制造商:Rochester Electronics LLC 功能描述:- Bulk
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