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參數(shù)資料
| 型號(hào)： | TVP3703-135 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Video Interface PALETTE Exract(雙PLL，先進(jìn)的視頻接口調(diào)色器) |
| 中文描述： | 視頻接口調(diào)色板Exract（雙鎖相環(huán)，先進(jìn)的視頻接口調(diào)色器） |
| 文件頁數(shù)： | 3/21頁 |
| 文件大?。?/td> | 427K |
| 代理商： | TVP3703-135 |
TVP3703
VIDEO INTERFACE PALETTE
TRUE-COLOR CMOS RAMDAC
SLAS100 – MARCH 1996
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions
micro port
TERMINAL
I/O
DESCRIPTION
NAME
NO.
5,
20
RD,
WR
I
Read enable and write enable. RD or WR control the timing of read and write operations on the micro port.
Most of the operations on the micro port can take place asynchronously to the pixel stream being processed
by the color palette. Various minimum periods between operations are specified (in terms of pixel clocks) to
allow this asynchronous behavior.
RD and WR should not be low at the same time.
RS0–RS2
21, 22,
50
I
Register select. RS0–RS2 specify which internal register is to be accessed. The RS0–RS2 inputs are sampled
on the falling edge of the active enable signal (RD or WR). Information on register access and contents is given
in the micro port section.
The additional RS2 signal allows access to the extended features without the need for performing an indirect
access sequence.
D0–D7
12–19
I/O
Input/output data. Data transfers between the 8-bit wide program data bus and the registers within the TVP3703
under control of the active enable signal (RD or WR).
In a write cycle, the rising edge of WR validates the data on the program data bus and causes it to be written
to the register selected.
The rising edge of RD signifies the end of a read cycle, after which the program data bus ceases to carry the
contents of the register addressed and goes to a high impedance state.
VS0–VS3
44–47
I
Video clock PLL select.VS0–VS3 select the frequency (default or user programmed) of the video clock PLL.
VS0–VS3 are ignored if the video clock frequency is selected by register control.
STROBE
43
I
Strobe input.The falling edge of STROBE latches VS0–VS3.
pixel port
TERMINAL
I/O
DESCRIPTION
NAME
PCLK
NO.
63
I
Pixel clock. The rising edge of PCLK controls the sampling of data on P0–P15, BLANK, and PIXMIX in all
modes.
P0–P15
1, 4, 23,
25,
52–59,
64–67
I
Pixel data word. The selected pixel mode determines how this pixel data is interpreted.
PIXMIX
24
I
Pixel mode select. PIXMIX controls the switching between primary and secondary pixel modes when the
extended pixel modes are selected (PIXMIX = 0 selects primary mode).
BLANK
11
I
Blank in. A low value sampled on BLANK, after the pipeline delay, turns the DAC outputs off.
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| TVP3703FN | VIDEO INTERFACE PALETTE TRUE-COLOR CMOS RAMDAC |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TVP3703-135CFN | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| TVP3703FN | 制造商:TI 制造商全稱:Texas Instruments 功能描述:VIDEO INTERFACE PALETTE TRUE-COLOR CMOS RAMDAC |
| TVP4020AGFN | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述: |
| TVP4020AGFN-8 | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述: |
| TVP5010 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:NTSC/PAL Video Decoder |
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