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參數(shù)資料
| 型號： | TVP3703FN |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | VIDEO INTERFACE PALETTE TRUE-COLOR CMOS RAMDAC |
| 中文描述： | VIDEO接口調(diào)色板真彩色的CMOS的RAMDAC |
| 文件頁數(shù)： | 6/21頁 |
| 文件大?。?/td> | 298K |
| 代理商： | TVP3703FN |
TVP3703
VIDEO INTERFACE PALETTE
TRUE-COLOR CMOS RAMDAC
SLAS100 – MARCH 1996
6
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
indexed register space
The TVP3703 indexed register space including the indexes, register contents, and values is shown in Table 3.
Table 3. Indexed Register Space
INDEX
INDEX REGISTER CONTENTS
VALUE
00 00h
Company ID = 97h
00 01h
Device ID = 03h
00 02h
Reserved (see Note 1)
00 03h
Primary pixel mode select
00 04h
Secondary pixel mode select
00 05h
Pipeline timing control
00 06h
Soft reset
00 07h
Power management A
00 08h
Power management B
00 09h –
00 1Fh
Reserved (see Note 1)
00 20h
VCLK V0 parameters low
(3Dh)
25 175
25.175
00 21h
VCLK V0 parameters high
(47h)
00 22h
VCLK V1 parameters low
(55h)
28 332
28.332
00 23h
VCLK V1 parameters high
(49h)
00 24h
VCLK V2 parameters low
(41h)
40 0
40.0
00 25h
VCLK V2 parameters high
(2Ah)
00 26h
VCLK V3 parameters low
(26h)
72 0
72.0
00 27h
VCLK V3 parameters high
(06h)
00 28h
VCLK V4 parameters low
(36h)
50 0
50.0
00 29h
00 2Ah
VCLK V4 parameters high
VCLK V5 parameters low
(26h)
(29h)
77 0
77.0
00 2Bh
VCLK V5 parameters high
(06h)
00 2Ch
VCLK V6 parameters low
(26h)
36 0
36.0
00 2Dh
VCLK V6 parameters high
(26h)
00 2Eh
VCLK V7 parameters low
(43h)
44 90
44.90
00 2Fh
VCLK V7 parameters high
(29h)
00 30h
VCLK V8 parameters low
(59h)
130 00
130.00
00 31h
VCLK V8 parameters high
(08h)
00 32h
VCLK V9 parameters low
(41h)
120 00
120.00
00 33h
Register power-up values for given synthesizer frequencies are shown in parentheses.
Synthesizer frequencies given for fI(XIN) = 14.31818 MHz
NOTE 1: Do not write to reserved locations
VCLK V9 parameters high
(06h)
INDEX
00 34h
INDEX REGISTER CONTENTS
VCLK V10 parameters low
VALUE
(41h)
80 0
80.0
00 35h
VCLK V10 parameters high
(0Ah)
00 36h
VCLK V11 parameters low
(56h)
31 50
31.50
00 37h
VCLK V11 parameters high
(48h)
00 38h
VCLK V12 parameters low
(43h)
110 0
110.0
00 39h
VCLK V12 parameters high
(07h)
00 3Ah
VCLK V13 parameters low
(59h)
65 0
65.0
00 3Bh
VCLK V13 parameters high
(28h)
00 3Ch
VCLK V14 parameters low
(28h)
75 0
75.0
00 3Dh
VCLK V14 parameters high
(06h)
00 3Eh
VCLK V15 parameters low
(40h)
94 50
94.50
00 3Fh
VCLK V15 parameters high
(08h)
00 40h
MCLK M0 parameters low
(3Dh)
45 0
45.0
00 41h
MCLK M0 parameters high
(28h)
00 42h
MCLK M1 parameters low
(51h)
66 0
66.0
00 43h
MCLK M1 parameters high
(27h)
00 44h
MCLK M2 parameters low
(2Ah)
70 0
70.0
00 45h
MCLK M2 parameters high
(07h)
00 46h
MCLK M3 parameters low
(36h)
80 0
80.0
00 47h
MCLK M3 parameters high
(08h)
00 48h
Clock synthesizer control
(00h)
00 49h –
FF D5h
Reserved (see Note 1)
FF D6h
CRC Test
FF D7h
CRC low byte
FF D8h
CRC high byte
FF D9h
Red, green, blue (RGB) DAC input
data test
FF DAh –
FF FFh
Reserved (see Note 1)
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