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參數(shù)資料
| 型號： | TVP5150AEVM |
| 廠商： | Texas Instruments |
| 文件頁數(shù)： | 2/74頁 |
| 文件大?。?/td> | 0K |
| 描述： | TVP5150AEVM |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 視頻，視頻解碼器 |
| 已用 IC / 零件： | TVP5150A |
| 主要屬性： | NTSC/PAL 數(shù)字視頻解碼器 |
| 次要屬性： | 圖形用戶接口，I²C 接口 |
| 已供物品： | 2 個板，線纜，CD，電源 |
| 配用： | 296-23058-ND - EVAL MODULE FOR DM642 |
| 相關(guān)產(chǎn)品： | TVP5150PBSR-ND - IC NTSC/PAL/SECAM DECODER 32TQFP TVP5150APBSRG4-ND - IC VIDEO DECODER 8BIT 32TQFP TVP5150AM1ZQCR-ND - IC VIDEO DECODER 8BIT 48BGA TVP5150AM1PBSRG4-ND - IC VIDEO DECODER 8BIT 32TQFP TVP5150AM1PBSG4-ND - IC VIDEO DECODER 8BIT 32TQFP 296-32781-ND - IC VIDEO DECODER 8BIT 32TQFP 296-32780-ND - IC VIDEO DECODER 8BIT 48BGA 296-27133-ND - IC VIDEO DECODER 8BIT 32TQFP 296-23026-6-ND - IC VIDEO DECODER 48-BGA 296-23025-6-ND - IC VIDEO DECODER 32-TQFP 更多... |
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15
Table 11. Terminal Functions (Continued)
TERMINAL
I/O
DESCRIPTION
NAME
NUMBER
I/O
DESCRIPTION
Digital Section
AVID
26
O
Active video indicator. This signal is high during the horizontal active time of the video output. AVID
toggling during vertical blanking intervals is controlled by bit 2 of the active video cropping start pixel
LSB register at address 12h (see Section 2.20.18).
DGND
19
I
Digital ground
DVDD
20
I
Digital supply. Connect to 1.8-V digital supply
FID/GLCO
23
O
FID: Odd/even field indicator or vertical lock indicator. For the odd/even indicator, a 1 indicates the odd
field.
GLCO: This serial output carries color PLL information. A slave device can decode the information to
allow chroma frequency control from the TVP5150A decoder. Data is transmitted at the SCLK rate in
Genlock mode. In RTC mode, SCLK/4 is used.
HSYNC
25
O
Horizontal synchronization signal
INTREQ/GPCL/
VBLK
27
I/O
INTREQ: Interrupt request output.
GPCL: General-purpose control logic. This terminal has two functions:
1. General-purpose output. In this mode the state of GPCL is directly programmed via I2C.
2. Vertical blank output. In this mode the GPCL terminal is used to indicate the vertical blanking interval
of the output video. The beginning and end times of this signal are programmable via I2C.
IO_DVDD
10
I
Digital supply. Connect to 3.3 V.
PDN
28
I
Power-down terminal (active low). Puts the decoder in standby mode. Preserves the value of the
registers.
RESETB
8
I
Active-low reset. RESETB can be used only when PDN = 1.
When RESETB is pulled low, it resets all the registers, restarts the internal microprocessor.
SCL
21
I/O
I2C serial clock (open drain)
PCLK/SCLK
9
O
System clock at either 1x or 2x the frequency of the pixel clock.
SDA
22
I/O
I2C serial data (open drain)
VSYNC/PALI
24
O
VSYNC: Vertical synchronization signal
PALI: PAL line indicator or horizontal lock indicator
For the PAL line indicator, a 1 indicates a noninverted line, and a 0 indicates an inverted line.
XTAL1
XTAL2
5
6
I
O
External clock reference. The user may connect XTAL1 to an oscillator or to one terminal of a crystal
oscillator. The user may connect XTAL2 to the other terminal of the crystal oscillator or not connect
XTAL2 at all. One single 14.31818-MHz crystal or oscillator is needed for ITU-R BT.601 sampling, for
all supported standards.
YOUT[6:0]
1218
I/O
Output decoded ITU-R BT.656 output/YCbCr 4:2:2 output with discrete sync.
YOUT(7)/I2CSEL
11
I/O
I2CSEL: Determines address for I2C (sampled during reset). A pullup or pulldown register is needed
(>1 k
) to program the terminal to the desired address.
1 = Address is 0xBA
0 = Address is 0xB8
YOUT7: MSB of output decoded ITU-R BT.656 output/YCbCr 4:2:2 output.
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