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參數(shù)資料
| 型號(hào)： | TWL2214CA |
| 英文描述： | High voltage fast-switching NPN power transistor |
| 中文描述： | 電源管理IC和鋰離子電池充電控制 |
| 文件頁數(shù)： | 18/36頁 |
| 文件大?。?/td> | 511K |
| 代理商： | TWL2214CA |
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SLVS321A
–
OCTOBER 2001
–
REVISED JANUARY 2002
18
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
I
2
C bus protocols
For normal data transfer, DATA is allowed to change only when CLK is low. Changes when CLK is high are
reserved for indicating the start and stop conditions. During data transfer, the data line must remain stable
whenever the clock line is high. There is one clock pulse per bit of data. Each data transfer is initiated with a
start condition and terminated with a stop condition. When addressed, the TWL2214CA device generates an
acknowledge bit after the reception of each byte. The master device (microprocessor) must generate an extra
clock pulse that is associated with the acknowledge bit. The TWL2214CA device must pull down the DATA line
during the acknowledge clock pulse so that the DATA line is a stable low during the high period of the
acknowledge clock pulse. The DATA line is a stable low during the high period of the acknowledge-related clock
pulse. Setup and hold times must be taken into account. During read operations, a master must signal the end
of data to the slave by not generating an acknowledge bit on the last byte that was clocked out of the slave. In
this case, the slave TWL2214CA device must leave the data line high to enable the master to generate the stop
condition.
Data line
stable;
data valid
DATA
CLK
Change
of data
allowed
Figure 7. Bit Transfer on the I
2
C Bus
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| TWL2214CAPFB | 制造商:Rochester Electronics LLC 功能描述:POWER SUPPLY MANAGEMENT IC:LION - Bulk 制造商:Texas Instruments 功能描述:CHGR LI-ION/LI-POL 150MA 2.8V 48TQFP - Tape and Reel |
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