參數(shù)資料
型號: TWR-MCF51MM
廠商: Freescale Semiconductor
文件頁數(shù): 40/57頁
文件大?。?/td> 0K
描述: TOWER SYSTEM BOARD MCF51MM
設(shè)計資源: TWR-MCF51MM Schematic
標準包裝: 1
系列: ColdFire®, Flexis™
類型: MCU
適用于相關(guān)產(chǎn)品: Freescale 電源塔系統(tǒng),MCF51MM
所含物品:
Electrical Characteristics
Freescale Semiconductor
45
3.13 SPI Characteristics
Table 23 and Figure 15 through Figure 18 describe the timing requirements for the SPI system.
Table 23. SPI Timing
No.1
1 Numbers in this column identify elements in Figure 15 through Figure 18.
Characteristic2
2 All timing is shown with respect to 20% VDD and 70% VDD, unless noted; 100 pF load on all SPI pins. All timing assumes slew
rate control disabled and high drive strength enabled for SPI output pins.
Symbol
Min
Max
Unit
C
1
Operating frequency
Master
Slave
fop
fBus/2048
0
fBus/2
fBus/4
Hz
D
2
SPSCK period
Master
Slave
tSPSCK
2
4
2048
tcyc
D
3
Enable lead time
Master
Slave
tLead
12
1
tSPSCK
tcyc
D
4
Enable lag time
Master
Slave
tLag
12
1
tSPSCK
tcyc
D
5
Clock (SPSCK) high or low time
Master
Slave
tWSPSCK
tcyc –30
tcyc – 30
1024 tcyc
ns
D
6
Data setup time (inputs)
Master
Slave
tSU
15
ns
D
7
Data hold time (inputs)
Master
Slave
tHI
0
25
ns
D
8
Slave access time3
3 Time to data active from high-impedance state.
ta
—1
tcyc
D
9
Slave MISO disable time4
4 Hold time to high-impedance state.
tdis
—1
tcyc
D
10
Data valid (after SPSCK edge)
Master
Slave
tv
25
ns
D
11
Data hold time (outputs)
Master
Slave
tHO
0
ns
D
12
Rise time
Input
Output
tRI
tRO
tcyc – 25
25
ns
D
13
Fall time
Input
Output
tFI
tFO
tcyc – 25
25
ns
D
MCF51MM256/128, Rev. 5
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