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參數(shù)資料
| 型號： | TZA1047HL/M2 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| 封裝： | 10 X 10 MM, 1.4 MM HEIGHT, PLASTIC, MS-026, SOT314-2, LQFP-64 |
| 文件頁數(shù)： | 27/69頁 |
| 文件大小： | 324K |
| 代理商： | TZA1047HL/M2 |
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9397 750 14664
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 1 June 2005
33 of 69
Philips Semiconductors
TZA1047
Preprocessor IC for CD and DVD rewritable
7.11.4 Radial servo signal block (normalizer sub-block)
The RAD block produces a normalized radial error signal REN. A detailed block diagram
of the RAD block is shown in Figure 18.
Signal REN is based on either 2 or 4 input currents selected by bit REN4/2 and bit DPD.
Setting bit DPD and bit REN4/2 both to logic 0 selects the associated tracking methods:
1-spot PP (4 segments), 3-spot CA or 3-spot PP. Setting bit DPD to logic 0 and REN4/2 to
logic 1 selects associated tracking method 1-spot PP (8 segments). For this method the
offset correction signal obtained from the lower branch is low-pass ltered before it is
added to the main normalized PP signal. An external capacitor named CCMPP,
connected to pin CMPP, denes the
3 dB frequency of the lter. If bit DPD = 1 the
tracking method is DPD, and REN is obtained from the difference between Q5 and Q6.
The polarity of signal REN is reversed if bit PREN is set to logic 1. If bit Q/NE = 0, signal
REN is available at servo output pin D3 and is also routed to the MON block for test
purposes. The relationship between the REN signal components is shown in Table 17.
An additional signal XDN (normalized spot position) is generated based on 3-spot PP,
1-spot PP (4 segments) or 1-spot PP (8 segments). The XDN signal can be inverted by
setting bit PXDN to logic 1. The XDN signal is also routed to the MON block for test
purposes.
Fig 18. RAD block.
001aab190
XDN
XDN to MON
DTDn
DTDp
+/
PXDN
+/
PREN
N
IDOC2
S4/8, CA/PP
Q1 to Q6
REN4/2, CA/PP
S4/8
RFCAL
rfcal
N
IDOC3
S4/8, CA/PP
Q1 to Q6
REN
REN to MON
DPD
+
LPF1
CMPP
Table 17:
REN signal (bit PREN = 0)
Bit S4/8
Bit CA/PP
Bit
REN4/2
Bit DPD
0
X
0
N[(Q1 + Q3), (Q2 + Q4)]
× GDOC × IN2
0110
N[(Q1 + Q3), (Q2 + Q4)]
× GDOC × IN2
1
X
0
N[Q5, Q6]
× GDOC × IN2
0010
N[(Q1 + Q3), (Q2 + Q4)]
× GDOC × IN2 + LPF1[N(Q5, Q6) × GDOC × IN3]
1
0
X
0
N[(Q1 + Q3 + Q6), (Q2 + Q4 + Q5)]
× GDOC × IN2
XXX1
DTDp DTDn
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