xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx
xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
9397
750
14664
K
oninklijk
e
Philips
Electronics
N.V
.2005.
All
r
ights
reser
v
ed.
Pr
oduct
data
sheet
Re
v
.02
—
1
J
une
2005
45
of
69
Philips
Semiconductor
s
TZA1047
Prepr
ocessor
IC
f
or
CD
and
D
VD
re
writab
le
All control bits are described in the various block descriptions.
The I2C-bus control register contains several bits that are intended only for test and evaluation purposes. These bits are
indicated in italics in the table, and should be set to logic 0.
Reserved values are not used and can be set to any value without affecting the circuit.
Normalizer
011001
19
25
S4/8
Q/NE
FEN4/2
PFEN
REN4/2
PREN
PXDN
RFCAL
011010
1A
26
ITR[3]
ITR[2]
ITR[1]
ITR[0]
ITW[3]
ITW[2]
ITW[1]
ITW[0]
011011
1B
27
OFW[3]
OFW[2]
OFW[1]
OFW[0]
OFR[3]
OFR[2]
OFR[1]
OFR[0]
011100
1C
28
IN2[3]
IN2[2]
IN2[1]
IN2[0]
IN1[3]
IN1[2]
IN1[1]
IN1[0]
011101
1D
29
CLMP
RTLN
PTLN
reserved
IN3[3]
IN3[2]
IN3[1]
IN3[0]
011110
1E
30
reserved
IN4[3]
IN4[2]
IN4[1]
IN4[0]
CANORM
011111
1F
31
BWRS
VARP
reserved
MIR1/2
IMIR[3]
IMIR[2]
IMIR[1]
IMIR[0]
ALFA
100000
20
32
reserved
ALF1/2
reserved
SQRT
reserved
IAN[1]
IAN[0]
BETA
100001
21
33
IBS[4]
IBS[3]
IBS[2]
IBS[1]
IBS[0]
BCTL[2]
BCTL[1]
BCTL[0]
Monitor
100010
22
34
MSEL[7]
MSEL[6]
MSEL[5]
MSEL[4]
MSEL[3]
MSEL[2]
MSEL[1]
MSEL[0]
EFMTIM
100011
23
35
TIM2[2]
TIM2[1]
TIM2[0]
TIM0[4]
TIM0[3]
TIM0[2]
TIM0[1]
TIM0[0]
100100
24
36
reserved
TIM1[5]
TIM1[4]
TIM1[3]
TIM1[2]
TIM1[1]
TIM1[0]
100101
25
37
reserved
TIM4[3]
TIM4[2]
TIM4[1]
TIM4[0]
TIM3[2]
TIM3[1]
TIM3[0]
100110
26
38
TIM9[1]
TIM9[0]
TIM8[2]
TIM8[1]
TIM8[0]
TIM5[2]
TIM5[1]
TIM5[0]
100111
27
39
ENRW
ENRS
ENALF
L/T
reserved
SMPLON
P/L
RST
101000
28
40
reserved
EFMINT
EFMTST
EFMON
reserved
FW
FR
RF AMP
101001
29
41
KEQ
ENEQ
ENNF
REFON
DIFFW
DIFFR
LDRF[1]
LDRF[0]
101010
2A
42
GRFR[3]
GRFR[2]
GRFR[1]
GRFR[0]
GRFW[3]
GRFW[2]
GRFW[1]
GRFW[0]
101011
2B
43
HA
BWRF[6]
BWRF[5]
BWRF[4]
BWRF[3]
BWRF[2]
BWRF[1]
BWRF[0]
101100
2C
44
VWRF[3]
VWRF[2]
VWRF[1]
VWRF[0]
VRRF[3]
VRRF[2]
VRRF[1]
VRRF[0]
101101
2D
45
DRVON
5X
OFFRFR[5]
OFFRFR[4] OFFRFR[3] OFFRFR[2] OFFRFR[1] OFFRFR[0]
101110
2E
46
reserved
OFFRFW[5]
BWRFW[4]
BWRFW[3]
BWRFW[2]
BWRFW[1]
BWRFW[0]
Miscellaneous
101111
2F
47
STBY
reserved
TSTDPD2
TSTDPD1
TSTVRF
TST[2]
TST[1]
TST[0]
Table 24:
Register denitions …continued
BLOCK
SUB-ADDR.
[5:0]
HEX
ADDR.
DEC.
ADDR.
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0