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參數(shù)資料
| 型號： | TZA1047HL/M3 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| 封裝： | 10 X 10 MM, 1.4 MM HEIGHT, PLASTIC, MS-026, SOT314-2, LQFP-64 |
| 文件頁數(shù)： | 57/69頁 |
| 文件大?。?/td> | 324K |
| 代理商： | TZA1047HL/M3 |
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9397 750 14664
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 1 June 2005
60 of 69
Philips Semiconductors
TZA1047
Preprocessor IC for CD and DVD rewritable
[1]
With the M1A, M1B and M2 versions negative segment input offset voltages, on pins VIA to VIH, are clipped to zero current internally
and hence cannot be compensated with IOA to IOH. With the M3 version negative input offset voltages are not clipped and can,
therefore, be compensated.
[2]
To allow the maximum differential input voltage range requires a VREF value greater than 2 V.
[3]
Invalid bit combination; do not use.
[4]
The input for the BETA circuit will be described in terms of a test signal, which is similar, but not identical, to the actual EFM signal used
in the application. The AC part of the test signal is a clipped sinusoidal signal with period (10T) 2-N and at top/bottom of (T/2) 2-N, with
N = 0 to 5 and T = 231 ns. It has a positive peak level Ip1 = {rf LPF(rf)}peak and a negative peak level Ip2 = {LPF(rf) rf}peak, which are
equal for the test version. The AC part is superimposed on a DC-level I0. Furthermore IBS[4:0] =19h, r/w = 1.
[5]
To save power, the BETA block and its DAC can be switched off completely by setting parameter BCTL[2:0] to 111. If the BETA block and
its DAC are switched off, the
3 dB frequency and time constant will not be dened.
10. Application information
10.1 Application circuit
Figure 28 shows an application diagram and the essential external components and basic
connections for use with PNX7850 (Centaurus1) and PNX7860 (Centaurus2) decoder
ICs. Changes may be made to the circuit to suit the system architecture.
When using TZA1047 versions M1A, M1B and M2 in applications using the Philips
PAEDIC based OPU (with current outputs), the input channels must have 15 k
pull-up
resistors connected to the 3.3 V supply line. These resistors are added so that negative
offsets do not appear on the TZA1047 inputs; see Table 27.
TCLK
clock period
60
-
ns
tSU;LD
set-up time load pulse
45
-
ns
tHIGH;LD
load pulse HIGH time
20
-
ns
Table 27:
Characteristics …continued
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
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