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參數(shù)資料
| 型號： | TZA3004 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | SDH/SONET STM1/OC3 and STM4/OC12 transceiver |
| 中文描述： | SDH / SONET的STM1/OC3和STM4/OC12收發(fā)器 |
| 文件頁數(shù)： | 12/28頁 |
| 文件大?。?/td> | 127K |
| 代理商： | TZA3004 |
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2000 Feb 17
12
Philips Semiconductors
Product specification
SDH/SONET STM1/OC3 and STM4/OC12
transceiver
TZA3005H
Table 6
Truth table operating modes
Note
1.
SD denotes either pin 22 (SDTTL) or pin 23 (SDPECL) (signal present = active = 1; loss of signal = inactive = 0).
During a loss of signal, the outputs RXPD0 to RXPD7 are forced to zero (see Table 5).
ALTPIN
(pin 50)
TEST1
(pin 10)
TEST2
(pin 11)
TEST3
(pin 13)
BUSWIDTH
(pin 30)
MODE
(pin 49)
SD
(1)
LLEN
(pin 31)
DLEN
(pin 32)
FUNCTIONAL
OPERATING MODE
0
X
X
0
X
0
X
1
1
normal operation
(STM1 byte/nibble)
squelched clock
operation
(STM4 byte)
normal operation
(STM4 byte)
normal operation
(STM4 byte)
loop timing
normal operation
loop timing
squelched clock
operation
normal operation
diagnostic loopback
line loopback
0
X
X
0
0
1
0
1
1
0
X
X
0
0
1
1
1
1
0
X
X
0
1
1
X
1
1
0
1
1
1
X
0
0
0
X
0
0
1
1
0
1
0
X
X
X
X
X
X
X
X
X
X
X
0
1
1
1
1
1
1
1
1
1
X
X
0
X
X
1
X
X
0
X
X
X
X
X
X
X
X
1
X
X
1
X
0
1
0
X
Receiver frame alignment
Figure 3 shows a typical frame and boundary alignment
sequence. Frame and byte boundary detection is enabled
ontherisingedgeofOOFandremainsenabledwhileOOF
is HIGH. Byte boundaries are recognized after the third A2
byte is received. FP goes HIGH for one RXPCLK cycle to
indicate that this is the first data byte with the correct byte
alignment on the output parallel data bus
(RXPD0 to RXPD7).
When interfaced with a section terminating device, OOF
must remain HIGH for a full frame period after the initial
frame pulse (FP). This is to allow the section terminating
device to internally verify that frame and byte alignment
are correct (see Fig.4). Because at least one frame pattern
will have been detected since the rising edge of OOF,
boundary detection is disabled when OOF goes LOW.
The frame and byte boundary detection block is activated
ontherisingedgeofOOF,andremainsactiveuntilaframe
pulse (FP) occurs and OOF goes LOW, whichever occurs
last. Figure 4 shows a typical OOF timing pattern when the
TZA3005H is connected to a down stream section
terminating device. OOF stays HIGH for one full frame
after the first frame pulse (FP). The frame and byte
boundary detection block is active until OOF goes LOW.
Figure 5 shows frame and byte boundary detection
activated on the rising edge of OOF, and deactivated by
the first frame pulse (FP) after OOF goes LOW.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TZA3004HL | SDH/SONET data and clock recovery unit STM1/4 OC3/12 |
| X00602 | SENSITIVE GATE SCR |
| X00602MA | 0.8A SCRs |
| X00602MA1AA2 | 0.8A SCRs |
| X00602MA2AL2 | 0.8A SCRs |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TZA3004HL | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:SDH/SONET data and clock recovery unit STM1/4 OC3/12 |
| TZA3005 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:SDH/SONET STM1/OC3 and STM4/OC12 transceiver |
| TZA3005H | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:SDH/SONET STM1/OC3 and STM4/OC12 transceiver |
| TZA3011A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:30 Mbits/s up to 3.2 Gbits/s A-rate(TM) laser drivers |
| TZA3011AVH/C2,551 | 功能描述:激光驅(qū)動器 3.3V D-LOOP LASERDRVR DC-3.2GB RoHS:否 制造商:Micrel 數(shù)據(jù)速率:4.25 Gbps 工作電源電壓:3 V to 3.6 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-16 封裝:Tube |
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