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參數(shù)資料
| 型號(hào)： | TZA3004 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | SDH/SONET STM1/OC3 and STM4/OC12 transceiver |
| 中文描述： | SDH / SONET的STM1/OC3和STM4/OC12收發(fā)器 |
| 文件頁(yè)數(shù)： | 22/28頁(yè) |
| 文件大小： | 127K |
| 代理商： | TZA3004 |
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2000 Feb 17
22
Philips Semiconductors
Product specification
SDH/SONET STM1/OC3 and STM4/OC12
transceiver
TZA3005H
Forward clocking
It is sometimes necessary to ‘forward clock’ data in an
SDH/SONET system. When this is the case, the input
parallel data clock (TXPCLK) and the reference clock
(REFCLK/REFCLKQ) from which the high speed serial
clockissynthesizedwillbothoriginatefromthesameclock
source. This section explains how to configure the
TZA3005H to operate in this mode.
The connections required for forward clocking are shown
in Fig.13. There are no timing specifications for the phase
relationship between REFCLK and TXPCLK.
The TZA3005H can handle any phase relationship
between these two input clocks if they are derived from the
same clock source. The TZA3005H internal transmitter
logic must be synchronized by asserting a master reset
(MRST).
Reverse clocking
In many cases, a reverse clocking scheme is used where
the upstream logic is clocked by the TZA3005H using
SYNCLKDIV (see Fig.14). There is no requirement
specification for the propagation delay from SYNCLKDIV
to TXPCLK because the TZA3005H can handle any phase
relationship between these two signals. The TZA3005H
internal transmitter logic must be synchronized by
asserting a master reset (MRST).
PECL output termination
The PECL outputs have to be terminated with 50
connected to V
CC
2.0 V. If this voltage is not available, a
Thevenin termination can be used as shown in Figs 11
and 12.
handbook, halfpage
VCC = 5.0 V
GND
MGK654
R2
83.3
R1
83.3
R4
125
R3
125
TXSD/TXSCLK
TXSDQ/TXSCLKQ
Fig.11 PECL output termination scheme
(V
CC
= 5.0 V).
handbook, halfpage
VCC = 3.3 V
GND
MGS978
R2
127
R1
127
R4
82.5
R3
82.5
TXSD/TXSCLK
TXSDQ/TXSCLKQ
Fig.12 PECL output termination scheme
(V
CC
= 3.3 V).
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TZA3004HL | SDH/SONET data and clock recovery unit STM1/4 OC3/12 |
| X00602 | SENSITIVE GATE SCR |
| X00602MA | 0.8A SCRs |
| X00602MA1AA2 | 0.8A SCRs |
| X00602MA2AL2 | 0.8A SCRs |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TZA3004HL | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:SDH/SONET data and clock recovery unit STM1/4 OC3/12 |
| TZA3005 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:SDH/SONET STM1/OC3 and STM4/OC12 transceiver |
| TZA3005H | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:SDH/SONET STM1/OC3 and STM4/OC12 transceiver |
| TZA3011A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:30 Mbits/s up to 3.2 Gbits/s A-rate(TM) laser drivers |
| TZA3011AVH/C2,551 | 功能描述:激光驅(qū)動(dòng)器 3.3V D-LOOP LASERDRVR DC-3.2GB RoHS:否 制造商:Micrel 數(shù)據(jù)速率:4.25 Gbps 工作電源電壓:3 V to 3.6 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-16 封裝:Tube |
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