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參數(shù)資料
| 型號： | TZA3015HW |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | 30 Mbit/s to 3.2 Gbit/s A-rate 4-bit fibre optic transceiver |
| 中文描述： | TRANSCEIVER, PQFP100 |
| 封裝： | 14 X 14 MM, 1 MM HEIGHT, SOT-638-1, HTQFP-100 |
| 文件頁數(shù)： | 2/67頁 |
| 文件大?。?/td> | 352K |
| 代理商： | TZA3015HW |
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2003 Dec 16
2
Philips Semiconductors
Preliminary specification
30 Mbit/s to 3.2 Gbit/s A-rate
4-bit fibre optic transceiver
TZA3015HW
FEATURES
General
A-rabitte
(1)
: supports any bit rate from 30 Mbit/s to
3.2 Gbit/s with one single reference frequency
4-bit parallel interface
Selectable Double Data Rate (DDR, half clock rate) or
Single Data Rate (SDR) clocking scheme on parallel
interface, enabling easy interfacing with FPGA devices
I
2
C-bus and pin programmable
Six selectable reference frequency ranges
Transmitter, receiver and transceiver modes
Clean-up loop back mode
Line loop back mode
Diagnostic loop back mode
Serial loop timing mode
Single 3.3 V power supply.
Limiter
Limiting amplifier with typical 5 mV input sensitivity
Received Signal Strength Indicator (RSSI)
Loss Of Signal (LOS) indicator with adjustable threshold
Differential overvoltage protection.
Data and clock recovery and synthesizer
Supports any bit rate from 30 Mbit/s to 3.2 Gbit/s when
using I
2
C-bus interface
Supports eight pre-programmed (pin selectable) bit
rates:
– SDH/SONET rates at 155.52 Mbit/s, 622.08 Mbit/s,
2488.32 Mbit/s and 2666.06 Mbit/s
(STM16/OC48 + FEC)
– Gigabit Ethernet at 1250 Mbit/s and 3125 Mbit/s
– Fibre Channel at 1062.5 Mbit/s and 2125 Mbit/s.
Provides stable clock signal at LOS
Frequency lock indicator for DCR
Loss Of Lock (LOL) indicator for synthesizer
ITU-T compliant jitter tolerance for Data and Clock
Recovery (DCR)
ITU-T compliant jitter transfer for DCR in clean-up loop
back mode
ITU-T compliant jitter generation for synthesizer.
Multiplexer
4 : 1 multiplexing ratio
Supports co-directional and contra-directional clocking
4-stage FIFO for wide tolerance to clock skew
Rail-to-rail parallel inputs compliant with LVPECL,
Current-Mode Logic (CML) and LVDS
Programmable parity checking
CML data and clock outputs.
Demultiplexer
1 : 4 demultiplexing ratio
Adjustable LVDS output swing
Frame detection for SDH/SONET and Gigabit Ethernet
(GE) frames.
I
2
C-bus configurable options
Programmable frequency resolution of 10 Hz
Independent receive and transmit bit rate
Slice level adjustment to improve Bit Error Rate (BER)
Six reference frequency ranges
Adjustable swing for CML serial data and clock outputs
Programmable polarity of RF I/Os
Clock versus data swap for optimum connectivity
Swap of parallel bus for optimum connectivity
Mute function for a forced logic 0 output state
Programmable parity
Programmable 32-bit frame detection.
(1) A-rate is a trademark of Koninklijke Philips Electronics N.V.
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| TZA3017HW | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:30 Mbits/s up to 3.2 Gbits/s A-rate fibre optic transmitter |
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