參數資料
型號: TZA3015HW
廠商: NXP SEMICONDUCTORS
元件分類: 數字傳輸電路
英文描述: 30 Mbit/s to 3.2 Gbit/s A-rate 4-bit fibre optic transceiver
中文描述: TRANSCEIVER, PQFP100
封裝: 14 X 14 MM, 1 MM HEIGHT, SOT-638-1, HTQFP-100
文件頁數: 26/67頁
文件大?。?/td> 352K
代理商: TZA3015HW
2003 Dec 16
26
Philips Semiconductors
Preliminary specification
30 Mbit/s to 3.2 Gbit/s A-rate
4-bit fibre optic transceiver
TZA3015HW
handbook, full pagewidth
MCE419
PHASE
FREQUENCY
DETECTOR
I
2
C bit:
CLUPPLLINV
I
2
C bit:
CLUPPLLHG
CHARGE
PUMP
IPUMP
from
DCR
CREF
C1
R
C2
VCXO
e.g. Vectron
VDSGLA type
REFERENCE
DIVIDER
to
synthesizer
external components
Fig.20 Clean-up PLL application with the TZA3015HW.
handbook, full pagewidth
MCE420
4
4
4
4
4
SYNTHESIZER
MULTIPLEXER
parallel
data
parallel
clock
parallel
data
parallel
clock
serial
data
serial
data
serial
clock
DEMULTIPLEXER
DCR
LIMITER
data
clock
data
clock
Fig.21 Clean-up loop back mode.
I/O configuration
LVDS
OUTPUTS
Several options exist that allow flexible configuration of the
LVDSoutputs: output amplitude, signal polarity,bus order,
mute and selective enable/disable of various outputs. All
theseoptionscanbesetintheregistersMFOBCON(A4h),
DMXCON (B8h), RXMFOUTC0 (D4h), DDR&RXPRSCL
(D5h) and TXMFOUTC (F2h). Affected by these registers
are:
Parallel clock output; pins RXPC(Q)
Parallel data output; pins RXPD0(Q) to RXPD3(Q)
Frame pulse output; pins RXFP(Q)
Parity output; pins RXPAR(Q)
Parity error output; pins TXPARERR(Q)
Transmitter parallel clock output; pins TXPCO(Q)
Prescaler DCR output; pins RXPRSCL(Q)
Prescaler synthesizer output; pins TXPRSCL(Q).
The output swing of all LVDS outputs can be set by pin
LOWSWING or by programming bit LOWSWING in
register MFOBCON (A4h). I
2
C-bus control is enabled by
programming bit I2CLOWSWING in register MFOBCON
(A4h).ThetypicalvoltagelevelsaregiveninTable 19.See
also Figs 34 and 35.
Table 19
Truth table for pin LOWSWING
LOWSWING
LVDS OUTPUT VOLTAGE SWING
LOW
HIGH
500 mV
300 mV
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