參數(shù)資料
型號(hào)： TZA3015HW
廠商： NXP SEMICONDUCTORS
元件分類(lèi)： 數(shù)字傳輸電路
英文描述： 30 Mbit/s to 3.2 Gbit/s A-rate 4-bit fibre optic transceiver
中文描述： TRANSCEIVER, PQFP100
封裝： 14 X 14 MM, 1 MM HEIGHT, SOT-638-1, HTQFP-100
文件頁(yè)數(shù)： 51/67頁(yè)
文件大?。?/td> 352K
代理商： TZA3015HW
2003 Dec 16
51
Philips Semiconductors
Preliminary specification
30 Mbit/s to 3.2 Gbit/s A-rate
4-bit fibre optic transceiver
TZA3015HW
V
i(p-p)
input voltage
swing
(peak-to-peak
value)
differential
hysteresis input
voltage
differential input
impedance
hold time
co-directional
clocking
set-up time
co-directional
clocking
hold time contra-
directional
clocking
set-up time
contra-directional
clocking
hold time
co-directional
clocking in DDR
mode
single-ended; note 6
1000
mV
V
i(hys)
T
amb
= 0
°
C to 85
°
C
T
amb
=
40
°
C to 0
°
C
25
15
mV
mV
z
i(dif)
80
100
120
t
h(co)
see Fig.29
150
300
ps
t
su(co)
see Fig.29
20
300
ps
t
h(contra)
see Fig.29
1100
850
ps
t
su(contra)
see Fig.29
1300
1450
ps
t
h(co)DDR
f
bit
= 124 to 800 Mbit/s;
see Fig.29
f
bit
= 30 to 124 Mbit/s;
see Fig.29; note 6
f
bit
= 124 to 800 Mbit/s;
see Fig.29
f
bit
= 30 to 124 Mbit/s;
see Fig.29; note 6
see Fig.29
0.3T
clk
+ 40
0.3T
clk
+ 240
ps
4780
5000
ps
t
su(co)DDR
set-up time
co-directional
clocking in DDR
mode
1
/
4
T
clk
130
1
/
4
T
clk
+ 200
ps
4560
3700
ps
t
h(contra)DDR
hold time
contra-directional
clocking in DDR
mode
set-up time
contra-directional
clocking in DDR
mode
duty cycle clock
TXPC(Q)
1
/
4
T
clk
1200
1
/
4
T
clk
1000
ps
t
su(contra)DDR
see Fig.29
1
/
4
T
clk
+ 1400
1
/
4
T
clk
+ 1600
ps
δ
note 6
40
50
60
%
Reference frequency input; pins CREF(Q)
V
i(p-p)
input swing
(peak-to-peak
value)
input voltage
range
input impedance
single-ended
50
1000
mV
V
i
note 6
V
CC
1
V
CC
+ 0.25
V
Z
i
single-ended to V
CC
40
50
60
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
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