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參數(shù)資料
| 型號(hào)： | UC3827Q-1 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | 1 A SWITCHING CONTROLLER, 500 kHz SWITCHING FREQ-MAX, PQCC28 |
| 封裝： | PLASIC, LCC-28 |
| 文件頁數(shù)： | 13/16頁 |
| 文件大?。?/td> | 391K |
| 代理商： | UC3827Q-1 |
I
RT +
2.5 V
R
RT
(3)
SLUS365D
– APRIL 1999 – REVISED APRIL 2011
Terminal Functions (continued)
TERMINAL
I/O
DESCRIPTION
N or
NAME
Q
DW
Ground referenced output to drive an N-channel MOSFET. The PULL and the PUSH outputs are driving
PUSH
24
28
O
the two switches of the push-pull converter with complementary signals at close to a 50% duty cycle.
Any undervoltage faults disables PUSH to an off condition (low).
The RAMP voltage, after a 700 mV internal level shift, is fed to the noninverting input of the buck PWM
comparator. A resistor to VIN and a capacitor to GND provide an input voltage feedforward signal for the
buck controller in voltage mode control. In peak current mode control, the RAMP pin receives the
RAMP
5
6
I
current signal of the buck converter. In an average current mode setup, the RAMP pin has a linearly
increasing ramp signal. This waveform may be generated either by connecting RAMP directly to CT, or
by connecting both a resistor from VCC to RAMP and a capacitor from RAMP to GND.
The output of the +5V on board reference. Bypass this pin with a capacitor to GND. The reference is off
REF
15
16
O
when the chip is in undervoltage lockout mode.o
A resistor to GND programs the charge current of the timing capacitor connected to CT. The charge
current approximately equals that shown in equation(3). The charge current should be less than 500
A
RT
17
19
I
to keep CT's discharge peak current less than 20 mA, which is CT's maximum practical discharge value.
The discharge time, which sets the maximum duty cycle, is set internally and is influenced by the charge
current.
The source connection for the floating buck switch. The voltage on the SRC pin can exceed VCC but
SRC
3
4
I
must be lower than 90 V
–VVCC. Also, during turn-off transients of the buck switch, the voltage at SRC
can go to
–2V.
5Soft-start pin requires a capacitor to GND. During soft-start the output of the voltage error amplifier is
SS
4
5
O
clamped to the soft-start capacitor voltage which is slowly charged by an internal current source. In
UVLO, SS is held low.
A bidirectional pin for the oscillator., used to synchronize several chips to the fastest oscillator. Its input
synchronization threshold is 1.4 V. The SYNC voltage is 3.6 V when the oscillator capacitor, CT, is
SYNC
19
21
I
discharged. Otherwise it is 0 V. If the recommended synchronization circuit is not used, a 1 k
or lower
value resistor from SYNC to GND may be needed to increase the fall time of the signal at SYNC.
A voltage source connected to this pin supplies the power for the UC3827. It is recommended to bypass
VCC
23
27
I
this pin to both GND and PGND ground connections with good quality high frequency capacitors
VEA+
14
15
I
Non-inverting input of the voltage error amplifier
VEA-
16
18
I
Inverting input of the voltage error amplifier
VEAO
10
11
O
Output of the voltage error amplifier
Supply voltage for the buck output. The floating driver of the UC3827 uses the bootstrap technique
which requires a reservoir capacitor to store the required energy for the on time of the buck switch. A
V+
1
I
diode must be connected from VCC to V+ to charge the reservoir capacitor. This diode must be able to
withstand VIN. The reservoir capacitor must be connected between V+ and SRC.
6
Copyright
1999–2011, Texas Instruments Incorporated
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