參數(shù)資料
型號(hào)： UCD9240RHBR
廠商： Texas Instruments, Inc.
英文描述： UCD9240 Digital Point of Load System Controller
中文描述： UCD9240系列數(shù)字點(diǎn)系統(tǒng)控制器的負(fù)荷
文件頁(yè)數(shù)： 10/21頁(yè)
文件大?。?/td> 572K
代理商： UCD9240RHBR
UCD9240
Digital Point of Load System Controller
Digital Inputs/Outputs
SLUS766
– APRIL 2007
10
www.ti.com
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
OL
Low-level output voltage
I
OH
= +6 mA
3
, V
33DIO
= 3.0 V
Dgnd
+ 0.25
V
V
OH
High-level output voltage
I
OH
= -6 mA
4
, V
33DIO
= 3.0 V
V
33dio
– 0.6
V
VIH
High-level input voltage
V33DIO = 3.0 V
2.1
V
VIL
Low-level input voltage
V33DIO = 3.5 V
1.0
V
PMBus/SMBus/I2C
The timing characteristics and timing diagram for the communications interface that supports I
2
C, SMBus and
PMBus is shown below.
Table 1 I
2
C/SMBus/PMBus Timing Characteristics
T
A
= -40
°
C to 85
°
C, 3.0V < V
DD
< 3.6V; Typical values at T
A
= 25
°
C and V
CC
= 2.5V (Unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
FSMB SMBus/PMBus operating frequency
Slave mode, SMBC 50% duty cycle
10
100
kHz
FI2C I
2
C operating frequency
Slave mode, SCL 50% duty cycle
10
400
kHz
FMAS SMBus master clock frequency
Master mode, No clock low slave extend
51.2
kHz
t
(BUF)
Bus free time between start and stop
4.7
us
t
(HD:STA)
Hold time after (repeated) start
4.0
us
t
(SU:STA)
Repeated start setup time
4.7
us
t
(SU:STO)
Stop setup time
4.0
us
Receive Mode
0
ns
t
(HD:DAT)
Data hold time
Transmit Mode
300
ns
t
(SU:DAT)
Data setup time
250
ns
t
(TIMEOUT)
Error signal/detect
See (5) below
25
35
us
t
(LOW)
Clock low period
4.7
us
t
(HIGH)
Clock high period
See (6) below
4.0
50
us
t
(LOW:SEXT)
Cumulative clock low slave extend time
See (7) below
25
us
t
(LOW:MEXT)
Cumulative clock low master extend time
See (8) below
10
us
t
f
Clock/data fall time
See (9) below
300
ns
t
r
Clock/data rise time
See (10) below
1000
ns
3
The maximum total current, IOHmax and IOLmax, for all outputs combined, should not exceed
+/-
12 mA to hold the maximum voltage
drop specified.
4 The maximum total current, IOHmax and IOLmax, for all outputs combined, should not exceed +/-48 mA to hold the maximum voltage drop specified.
5
The UCD9110 times out when any clock low exceeds t
(TIMEOUT)
.
6
t
(HIGH)
, Max, is the minimum bus idle time. SMBC = SMBD = 1 for t > 50 ms causes reset of any transaction involving UCD9110 that is in
progress. This specification is valid when the NC_SMB control bit remains in the default cleared state (CLK[0]=0).
7
t
(LOW:SEXT)
is the cumulative time a slave device is allowed to extend the clock cycles in one message from initial start to the stop.
8
t
(LOW:MEXT)
is the cumulative time a master device is allowed to extend the clock cycles in one message from initial start to the stop.
9
Rise time t
r
= VILMAX – 0.15) to (VIHMIN + 0.15)
10
Fall time t
f
= 0.9V
DD
to (VILMAX – 0.15)
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