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參數(shù)資料
| 型號(hào)： | UCD9240RHBR |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | UCD9240 Digital Point of Load System Controller |
| 中文描述： | UCD9240系列數(shù)字點(diǎn)系統(tǒng)控制器的負(fù)荷 |
| 文件頁數(shù)： | 8/21頁 |
| 文件大小： | 572K |
| 代理商： | UCD9240RHBR |
UCD9240
Digital Point of Load System Controller
the external NPN connected to a pull up resistor and the VD33FB pin. The NPN emitter becomes the 3.3 V
supply for the chip and should be bypassed to ground with 4 to 5 uF.
Analog Inputs/Outputs
SLUS766
– APRIL 2007
8
www.ti.com
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Vsense Differential
Voltage Range
0.0
0.8
1.6
V
EAPn, EANn
Maximum Vsense
excursion
-0.3
2.0
V
Small Signal Error voltage
resolution
during start/stop ramp
during run mode
4.0
1.0
mV
mV
EAP-EAN
Error Voltage Accuracy
“DAC commanded to be 1V”
.99
1
1.01
V
Input impedance
ground reference
TBD
ohm
Input capacitance
differential
TBD
pF
I
BIAS
Bias current
PMBus Addr pins
9
11
uA
V
ADDR
PMBus Address
programming bins
See Table 2
0.141
2.50
uA
V
RANGE
: CSxx
voltage range for current
sense input
0
2.5
V
V
RANGE
: Vin, Vtrack,
Vtemp
input voltage range
0
2.5
V
V
OVERCURRENT
:
CS1-A, CS2-A,
CS3-A, CS4-A
Analog Overcurrent
Threshold
2.0
V
C
I
2
Current Sense Input
capacitance
5
10
pF
ADCRefIn
External Reference
(80-pin package)
(Not currently supported in the Firmware!)
1.8
V33A
V
Timing
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
T
retention
Retention of configuration
parameters
T
J
= 25C
100
Years
t
(reset)
Pulse length needed at
Reset
2
μ
S
Fault Detection Latency
t
(FAULT)
time to disable PWM
output
High level on FAULT pin
20
nS
t(CLF)
time to disable PWM
output
Step change in CS voltage from 1.0V to
2.5V
20
nS
t(OC)
time to disable PWM
output due to overcurrrent
detection on average KKK
Step change in CS voltage from 50% of
PMBus programmed over-current threshold
to 150% of threshold
800
uS
2
Not production tested. Limits verified by design.
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