參數(shù)資料
型號(hào)： UDA1384
廠商： NXP Semiconductors N.V.
英文描述： Multichannel audio coder-decoder
中文描述： 多聲道音頻編碼解碼器
文件頁(yè)數(shù)： 27/55頁(yè)
文件大小： 276K
代理商： UDA1384
9397 750 14366
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 17 January 2005
27 of 55
Philips Semiconductors
UDA1384
Multichannel audio coder-decoder
11.3 System settings
Table 22:
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
System register (address 00h) bit allocation
15
14
RST
VFS1
-
0
13
12
VCE
1
read and write
4
FS0
1
read and write
11
VAP
0
10
DSD
0
9
8
VFS0
0
SC1
0
SC0
0
7
6
5
3
2
1
0
OP1
0
OP0
0
FS1
0
ACE
1
ADP
0
DCE
1
DAP
0
Table 23:
Bit
15
Description of system register bits
Symbol
Description
RST
Reset.
Bit RST initializes the L3-bus registers with the default settings.
1 = Reset to default settings
0 = No reset
VFS[1:0]
Voice ADC sampling frequency.
A 2-bit value to select the voice ADC
sampling frequency. Default 00. See
Table 24
.
VCE
Voice ADC clock enable.
1 = clock enabled (default)
0 = clock disabled
VAP
Voice ADC power control
. Bit VAP is to reduce the power consumption of
the voice ADC.
1 = state is power-on
0 = state is power-off (default)
DSD
DSD mode selection.
Bit DSD selects the DSD mode.
1 = DSD mode
0 = normal mode (default)
SC[1:0]
System clock frequency.
A 2-bit value to select the used external clock
frequency. 128f
s
system clock for the DAC can be used by setting
bit DVD = 1. Default 00. See
Table 25
.
OP[1:0]
Operating mode selection.
A 2-bit value to select the operation mode of
the audio ADC and DAC. Default 00. See
Table 26
.
FS[1:0]
Sampling frequency.
A 2-bit value to select the sampling frequency of the
audio ADC and DAC in the WS mode. Default 01. See
Table 27
.
ACE
ADC clock enable.
Bit ACE enables the audio ADC clock
1 = clock enabled (default)
0 = clock disabled
ADP
ADC power control
. Bit ADP is to reduce the power consumption of the
audio ADC.
1 = state is power-on
0 = state is power-off (default)
14 to 13
12
11
10
9 to 8
7 to 6
5 to 4
3
2
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