參數(shù)資料
型號: UDA1384
廠商: NXP Semiconductors N.V.
英文描述: Multichannel audio coder-decoder
中文描述: 多聲道音頻編碼解碼器
文件頁數(shù): 39/55頁
文件大?。?/td> 276K
代理商: UDA1384
9397 750 14366
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 17 January 2005
39 of 55
Philips Semiconductors
UDA1384
Multichannel audio coder-decoder
11.13 Supplemental settings 1
11.14 Supplemental settings 2
Table 58:
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Supplemental settings 1 register (address 30h) bit allocation
15
14
13
-
-
-
0
0
0
12
-
0
read and write
4
-
0
read and write
11
-
0
10
-
0
9
-
0
8
-
0
7
6
-
0
5
-
0
3
-
0
2
-
0
1
-
0
0
-
0
PDT
0
Table 59:
Bit
15 to 8
7
Description of supplemental settings 1 register bits
Symbol
Description
-
default 0000 0000
PDT
Power down time.
Bit PDT selects the time of the SDAC power-down
sequence.
1 = 1024/f
s
seconds
0 = 512/f
s
seconds (default)
-
default 000 0000
6 to 0
Table 60:
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Supplemental settings 2 register (address 31h) bit allocation
15
14
13
-
-
-
0
0
0
12
-
0
read and write
4
DITH0
0
read and write
11
-
0
10
-
0
9
-
0
8
-
0
7
-
0
6
5
3
-
0
2
-
0
1
0
DITH2
0
DITH1
0
VMTP
0
PDLNA
0
Table 61:
Bit
15 to 7
6 to 4
Description of supplemental settings 2 register bits
Symbol
Description
-
default 0000 0000 0
DITH[2:0]
DAC dither control.
A 3-bit value to control the dithering of the SDAC.
Default 000. See
Table 62
.
-
default 00
VMTP
Voice mute period control.
Bit VMPT selects the voice ADC mute
period at power-up.
1 = mute for 1024 samples (1024/f
s
)
0 = mute for 2048 samples (2048/f
s
; default)
3 to 2
1
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