參數(shù)資料
型號: UDA1384
廠商: NXP Semiconductors N.V.
英文描述: Multichannel audio coder-decoder
中文描述: 多聲道音頻編碼解碼器
文件頁數(shù): 33/55頁
文件大?。?/td> 276K
代理商: UDA1384
9397 750 14366
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 17 January 2005
33 of 55
Philips Semiconductors
UDA1384
Multichannel audio coder-decoder
11.7 DAC channel selection
Table 38:
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
DAC channel select register (address 10h) bit allocation
15
14
13
MIX1
MIX0
MC5
0
0
0
12
MC4
0
read and write
4
CS4
0
read and write
11
MC3
0
10
MC2
0
9
8
MC1
0
MC0
0
7
6
5
3
2
1
0
SEL1
0
SEL0
0
CS5
0
CS3
0
CS2
0
CS1
0
CS0
0
Table 39:
Bit
15 to 14
Description of DAC channel select register bits
Symbol
Description
MIX[1:0]
DAC mixer setting.
A 2-bit value to enable the DAC mixer. Default 00.
See
Table 40
.
MC[5:0]
DAC mixing channel selection.
A group of 6 enable bits to make DAC
mixing channels ready for receiving feature settings through register
address 11h. Only selected registers accept new settings. Default 00 0000
(no channel ready). See
Table 41
.
SEL[1:0]
Feature selection.
A 2-bit value to select the features to be set through
register address 11h. When the feature settings are written, only selected
feature settings are changed and non selected features are kept
unchanged. Default 00. See
Table 42
.
CS[5:0]
DAC channel selection.
A group of 6 enable bits to make DAC channel
ready for receiving feature settings through register address 11h.
Default 00 0000 (no channel ready). See
Table 41
.
13 to 8
7 and 6
5 to 0
Table 40:
MIX1
DAC mixer setting bits
MIX0
0
1
0
1
Function
no mixing (default)
no mixing
mixing ADC 1
mixing ADC 2
0
0
1
1
Table 41:
MC5
CS5
0
0
:
0
:
1
DAC channel and mixing channel selection bits
MC4
MC3
MC2
MC1
CS4
CS3
CS2
CS1
0
0
0
0
0
0
0
0
:
:
:
:
0
1
0
1
:
:
:
:
1
1
1
1
MC0
CS0
0
1
:
0
:
1
Function
no channel ready (default)
channel 1 selected
channel 2 and channel 4 selected
all channels selected
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