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S3C2501X
PRODUCT OVERVIEW
1-31
Table 1-10. S3C2501X GDMA Controller
Registers
DPRIC
DPRIF
DPRIR
DCON0
DSAR0
DDAR0
DTCR0
DRER0
DIPR0
DCON1
DSAR1
DDAR1
DTCR1
DRER1
DIPR1
DCON2
DSAR2
DDAR2
DTCR2
DRER2
DIPR2
DCON3
DSAR3
DDAR3
DTCR3
DRER3
DIPR3
DCON4
DSAR4
DDAR4
DTCR4
DRER4
DIPR4
DCON5
DSAR5
DDAR5
DTCR5
DRER5
DIPR5
Address
0xF0051000
0xF0052000
0xF0053000
0xF0050000
0xF0050004
0xF0050008
0xF005000C
0xF0050010
0xF0050014
0xF0050020
0xF0050024
0xF0050028
0xF005002C
0xF0050030
0xF0050034
0xF0050040
0xF0050044
0xF0050048
0xF005004C
0xF0050050
0xF0050054
0xF0050060
0xF0050064
0xF0050068
0xF005006C
0xF0050070
0xF0050074
0xF0050080
0xF0050084
0xF0050088
0xF005008C
0xF0050090
0xF0050094
0xF00500A0
0xF00500A4
0xF00500A8
0xF00500AC
0xF00500B0
0xF00500B4
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
W
R/WC
R/W
R/W
R/W
R/W
W
R/WC
R/W
R/W
R/W
R/W
W
R/WC
R/W
R/W
R/W
R/W
W
R/WC
R/W
R/W
R/W
R/W
W
R/WC
R/W
R/W
R/W
R/W
W
R/WC
Description
Reset Value
0x00000000
0x00543210
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
GDMA priority configuration register
GDMA programmable priority register for fixed
GDMA programmable priority register for round-robin
GDMA channel 0 control register
GDMA channel 0 source address register
GDMA channel 0 destination address register
GDMA channel 0 transfer count register
GDMA channel 0 run enable register
GDMA channel 0 interrupt pending register
GDMA channel 1 control register
GDMA channel 1 source address register
GDMA channel 1 destination address register
GDMA channel 1 transfer count register
GDMA channel 1 run enable register
GDMA channel 1 interrupt pending register
GDMA channel 2 control register
GDMA channel 2 source address register
GDMA channel 2 destination address register
GDMA channel 2 transfer count register
GDMA channel 2 run enable register
GDMA channel 2 interrupt pending register
GDMA channel 3 control register
GDMA channel 3 source address register
GDMA channel 3 destination address register
GDMA channel 3 transfer count register
GDMA channel 3 run enable register
GDMA channel 3 interrupt pending register
GDMA channel 4 control register
GDMA channel 4 source address register
GDMA channel 4 destination address register
GDMA channel 4 transfer count register
GDMA channel 4 run enable register
GDMA channel 4 interrupt pending register
GDMA channel 5 control register
GDMA channel 5 source address register
GDMA channel 5 destination address register
GDMA channel 5 transfer count register
GDMA channel 5 run enable register
GDMA channel 5 interrupt pending register