參數(shù)資料
型號(hào)： UPD44323362
廠商： NEC Corp.
英文描述： 32M-BIT CMOS SYNCHRONOUS FAST STATIC RAM 1M-WORD BY 36-BIT HSTL INTERFACE / REGISTER-REGISTER / LATE WRITE
中文描述： 32兆位CMOS同步快速靜態(tài)RAM的100萬(wàn)字的36位HSTL接口/寄存器間/晚寫
文件頁(yè)數(shù)： 1/28頁(yè)
文件大?。?/td> 252K
代理商： UPD44323362
32M-BIT CMOS SYNCHRONOUS FAST STATIC RAM
1M-WORD BY 36-BIT
HSTL INTERFACE / REGISTER-REGISTER / LATE WRITE
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
DATA SHEET
MOS INTEGRATED CIRCUIT
μ
PD44323362
Document No. M16379EJ4V0DS00 (4th edition)
Date Published May 2004 NS CP(K)
Printed in Japan
The mark
ì
shows major revised points.
2002
Description
The
μ
PD44323362 is a 1,048,576 words by 36 bits synchronous static RAM fabricated with advanced CMOS
technology using Full-CMOS six-transistor memory cell.
The
μ
PD44323362 is suitable for applications which require high-speed, low voltage, high-density memory and wide
bit configuration, such as cache and buffer memory.
The
μ
PD44323362 is packaged in a 119-pin PLASTIC BGA (Ball Grid Array).
Features
Fully synchronous operation
HSTL Input / Output levels
Fast clock access time: 2.0 ns / 250 MHz
Asynchronous output enable control: /G
Byte write control: /SBa (DQa1 to DQa9), /SBb (DQb1 to DQb9), /SBc (DQc1 to DQc9), /SBd (DQd1 to DQd9)
Common I/O using three-state outputs
Internally self-timed write cycle
Late write with 1 dead cycle between Read-Write
User-configurable outputs: Controlled impedance outputs or push-pull outputs
Boundary scan (JTAG) IEEE 1149.1 compatible
2.5
±
0.125 V (Chip) / 1.4 to 1.9 V (I/O) supply
119 bump BGA package, 1.27 mm pitch, 14 mm
×
22 mm
Sleep mode: ZZ (Enables sleep mode, active high)
Ordering Information
Part number
Access time
Clock frequency
Package
μ
PD44323362F1-C40-FJ1
2.0 ns
250 MHz
119-pin PLASTIC BGA
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