參數資料
型號： UPD44323362
廠商： NEC Corp.
英文描述： 32M-BIT CMOS SYNCHRONOUS FAST STATIC RAM 1M-WORD BY 36-BIT HSTL INTERFACE / REGISTER-REGISTER / LATE WRITE
中文描述： 32兆位CMOS同步快速靜態(tài)RAM的100萬字的36位HSTL接口/寄存器間/晚寫
文件頁數： 14/28頁
文件大?。?/td> 252K
代理商： UPD44323362
14
Data Sheet M16379EJ4V0DS
μ
PD44323362
JTAG Specifications
The
μ
PD44323362 supports a limited set of JTAG functions as in IEEE standard 1149.1.
Test Access Port (TAP) Pins
Pin name
Pin assignments
Description
TCK
4 U
Test Clock Input. All input are captured on the rising edge of TCK and all outputs propagate
from the falling edge of TCK.
TMS
2 U
Test Mode Select. This is the command input for the TAP controller state machine.
TDI
3 U
Test Data Input. This is the input side of the serial registers placed between TDI and TDO.
The register placed between TDI and TDO is determined by the state of the TAP controller
state machine and the instruction that is currently loaded in the TAP instruction.
Test Data Output. Output changes in response to the falling edge of TCK. This is the output
side of the serial registers placed between TDI and TDO.
TDO
5 U
Remark
The device does not have TRST (TAP reset). The Test-Logic Reset state is entered while TMS is held high
for five rising edges of TCK. The TAP controller state is also reset on the SRAM POWER-UP.
JTAG DC Characteristics (T
j
= 5 to 110
°
C)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Note
JTAG input high voltage
V
IH
2.2
V
DD
+ 0.3 (3.0 V MAX)
V
JTAG input low voltage
V
IL
–0.3
+
0.5
V
JTAG output high voltage
V
OH
I
OH
= –8 mA
2.4
–
V
JTAG output low voltage
V
OL
I
OL
= 8 mA
–
0.4
V
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