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參數(shù)資料
| 型號： | UPD4481361GF-A65 |
| 廠商： | NEC Corp. |
| 英文描述： | 8M-BIT ZEROSB SRAM FLOW THROUGH OPERATION |
| 中文描述： | 800萬位ZEROSB SRAM的流動經(jīng)手術(shù) |
| 文件頁數(shù)： | 17/28頁 |
| 文件大?。?/td> | 326K |
| 代理商： | UPD4481361GF-A65 |
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17
Data Sheet M15561EJ3V0DS
μ
PD4481161, 4481181, 4481321, 4481361
Read and Write Cycle (3.3 V LVTTL Interface)
Parameter
Symbol
-A65
-A75
-A85
Unit
Note
-A65Y
-A75Y
-A85Y
(133 MHz)
(117 MHz)
(100 MHz)
Standard
Alias
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
Cycle time
TKHKH
TCYC
7.5
–
8.6
–
10
–
ns
Clock access time
TKHQV
TCD
–
6.5
–
7.5
–
8.5
ns
Output enable access time
TGLQV
TOE
–
3.5
–
3.5
–
3.5
ns
Clock high to output active
TKHQX1
TDC1
2.5
–
2.5
–
2.5
–
ns
1, 2
Clock high to output change
TKHQX2
TDC2
2.5
–
2.5
–
2.5
–
ns
Output enable to output active
TGLQX
TOLZ
0
–
0
–
0
–
ns
1
Output disable to output High-Z
TGHQZ
TOHZ
0
3.5
0
3.5
0
3.5
ns
1
Clock high to output High-Z
TKHQZ
TCZ
2.5
5
2.5
5
2.5
5
ns
1, 2
Clock high pulse width
TKHKL
TCH
2.5
–
2.5
–
2.5
–
ns
Clock low pulse width
TKLKH
TCL
2.5
–
2.5
–
2.5
–
ns
Setup times Address
TAVKH
TAS
1.5
–
1.5
–
2
–
ns
Address advance
TADVVKH
TADVS
Clock enable
TEVKH
TCES
Chip enable
TCVKH
TCSS
Data in
TDVKH
TDS
Write enable
TWVKH
TWS
Hold times
Address
TKHAX
TAH
0.5
–
0.5
–
0.5
–
ns
Address advance
TKHADVX
TADVH
Clock enable
TKHEX
TCEH
Chip enable
TKHCX
TCSH
Data in
TKHDX
TDH
Write enable
TKHWX
TWH
Power down entry time
TZZE
TZZE
–
7.5
–
8.6
–
10
ns
Power down recovery time
TZZR
TZZR
–
7.5
–
8.6
–
10
ns
Notes 1.
Transition is measured
±
200 mV from steady state.
2.
To avoid bus contention, the output buffers are designed such that TKHQZ (device turn-off) is faster than
TKHQX1 (device turn-on) at a given temperature and voltage. The specs as shown do not imply bus
contention because TKHQX1 is a min. parameter that is worse case at totally different conditions (T
A
min.,
V
DD
max.) than TKHQZ, which is a max. parameter (worse case at T
A
max., V
DD
min.).
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