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參數(shù)資料
| 型號(hào)： | UPD4482321GF-C85 |
| 廠商： | NEC Corp. |
| 英文描述： | 8M-BIT CMOS SYNCHRONOUS FAST SRAM FLOW THROUGH OPERATION |
| 中文描述： | 800萬位CMOS同步快速靜態(tài)存儲(chǔ)器流經(jīng)手術(shù) |
| 文件頁數(shù)： | 13/28頁 |
| 文件大?。?/td> | 370K |
| 代理商： | UPD4482321GF-C85 |
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13
μ
PD4482161, 4482181, 4482321, 4482361
Data Sheet M14521EJ3V0DS
DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)
Parameter
Symbol
Test condition
MIN.
TYP.
MAX.
Unit
Note
Input leakage current
I
LI
V
IN
(except ZZ, MODE) = 0 V to V
DD
–2
+2
μ
A
I/O leakage current
I
LO
V
I/O
= 0 V to V
DD
Q, Outputs are disabled.
–2
+2
μ
A
Operating supply current
I
DD
Device selected,
-A65
250
mA
Cycle = MAX.
-A65Y
V
IN
≤
V
IL
or V
IN
≥
V
IH
,
-A75, -C75
225
I
I/O
= 0 mA
-A75Y, -C75Y
-A85, -C85
200
-A85Y, -C85Y
I
DD1
Suspend cycle, Cycle = MAX.
150
/AC, /AP, /ADV, /GW, /BWEs
≥
V
IH
V
IN
≤
V
IL
or V
IN
≥
V
IH
, I
I/O
= 0 mA
Standby supply current
I
SB
Device deselected, Cycle = 0 MHz
30
mA
V
IN
≤
V
IL
or V
IN
≥
V
IH
, All inputs are static.
I
SB1
Device deselected, Cycle = 0 MHz
15
V
IN
≤
0.2 V or V
IN
≥
V
DD
–
0.2 V
V
I/O
≤
0.2 V, All inputs are static.
I
SB2
Device deselected, Cycle = MAX.
110
V
IN
≤
V
IL
or V
IN
≥
V
IH
Power down supply current
I
SBZZ
ZZ
≥
V
DD
– 0.2 V, V
I/O
≤
V
DD
Q + 0.2 V
15
mA
2.5 V LVTTL interface
High level output voltage
V
OH
I
OH
= –2.0 mA
1.7
V
I
OH
= –1.0 mA
2.1
Low level output voltage
V
OL
I
OL
= +2.0 mA
0.7
V
I
OL
= +1.0 mA
0.4
3.3 V LVTTL interface
High level output voltage
V
OH
I
OH
= –4.0 mA
2.4
V
Low level output voltage
V
OL
I
OL
= +8.0 mA
0.4
V
Capacitance (T
A
= 25 °C, f = 1 MHz)
Parameter
Symbol
Test condition
MIN.
TYP.
MAX.
Unit
Input capacitance
C
IN
V
IN
= 0 V
6.0
pF
Input / Output capacitance
C
I/O
V
I/O
= 0 V
8.0
pF
Clock input capacitance
C
clk
V
clk
= 0 V
6.0
pF
Remark
These parameters are periodically sampled and not 100
%
tested.
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