- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄379499 > UPD45128841G5-A80 (NEC Corp.) 128M-bit Synchronous DRAM 4-bank, LVTTL PDF資料下載
參數(shù)資料
| 型號(hào)： | UPD45128841G5-A80 |
| 廠商： | NEC Corp. |
| 英文描述： | 128M-bit Synchronous DRAM 4-bank, LVTTL |
| 中文描述： | 128兆位同步DRAM 4銀行，LVTTL |
| 文件頁(yè)數(shù)： | 12/92頁(yè) |
| 文件大?。?/td> | 1107K |
| 代理商： | UPD45128841G5-A80 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)當(dāng)前第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)
Data Sheet M12650EJBV0DS00
12
μ
PD45128441, 45128841, 45128163
Write command
(/CS, /CAS, /WE = Low, /RAS = High)
If the mode register is in the burst write mode, this command sets the
burst start address given by the column address to begin the burst
write operation. The first write data in burst mode can input with this
command with subsequent data on following clocks.
Fig.4
Column address and write command
/WE
/CAS
/RAS
/CS
CKE
CLK
H
Add
A10
BA0(A13), BA1(A12)
Col.
Read command
(/CS, /CAS = Low, /RAS, /WE = High)
Read data is available after /CAS latency requirements have been
met. This command sets the burst start address given by the column
address.
Fig.5
Column address and read command
/WE
/CAS
/RAS
/CS
CKE
CLK
H
Add
A10
BA0(A13), BA1(A12)
Col.
CBR (auto) refresh command
(/CS, /RAS, /CAS = Low, /WE, CKE = High)
This command is a request to begin the CBR (auto) refresh
operation. The refresh address is generated internally.
Before executing CBR (auto) refresh, all banks must be precharged.
After this cycle, all banks will be in the idle (precharged) state and
ready for a row activate command.
During t
RC
period (from refresh command to refresh or activate
command), the
μ
PD45128xxx cannot accept any other command.
Fig.6
CBR (auto) refresh command
Add
A10
BA0(A13), BA1(A12)
/WE
/CAS
/RAS
/CS
CKE
CLK
H
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| UPD45128841G5-A80-9JF | 128M-bit Synchronous DRAM 4-bank, LVTTL |
| UPD45128163G5-A10B | 128M-bit Synchronous DRAM 4-bank, LVTTL |
| UPD45128163G5-A10B-9JF | 128M-bit Synchronous DRAM 4-bank, LVTTL |
| UPD45128163G5-A75 | 128M-bit Synchronous DRAM 4-bank, LVTTL |
| UPD45128163G5-A75-9JF | 128M-bit Synchronous DRAM 4-bank, LVTTL |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| UPD4516161AG5A109NF | 制造商:NEC Electronics Corporation 功能描述: |
| UPD4516161AG5-A10-9NF | 制造商:NEC Electronics Corporation 功能描述:SDRAM, 1M x 16, 50 Pin, Plastic, TSOP |
| UPD4528BC | 制造商:Panasonic Industrial Company 功能描述:IC |
| UPD4528C | 制造商:Panasonic Industrial Company 功能描述:IC SUB:TC4528BP OR TVSTC4528BP |
| UPD4564163G5-A10B-9JF | 制造商:NEC Electronics Corporation 功能描述:SDRAM, 4M x 16, 54 Pin, Plastic, TSOP |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。