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參數(shù)資料
| 型號(hào)： | UPD4564323 |
| 廠商： | NEC Corp. |
| 英文描述： | 64M-bit Synchronous DRAM 4-bank, LVTTL |
| 中文描述： | 6400位同步DRAM 4銀行，LVTTL |
| 文件頁(yè)數(shù)： | 16/84頁(yè) |
| 文件大小： | 1048K |
| 代理商： | UPD4564323 |
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Data Sheet M14376EJ2V0DS00
16
μ
PD4564323 for Rev.
E
(3/3)
Current state
/CS /RAS /CAS /WE
Address
Command
Action
Notes
Write recovering
H
×
×
×
×
DESL
Nop
→
Enter row active after t
DPL
L
H
H
H
×
NOP
Nop
→
Enter row active after t
DPL
L
H
H
L
×
BST
Nop
→
Enter row active after t
DPL
L
H
L
H
BA, CA, A10
READ/READA
Start read, Determine AP
8
L
H
L
L
BA, CA, A10
WRIT/WRITA
New write, Determine AP
L
L
H
H
BA, RA
ACT
ILLEGAL
3
L
L
H
L
BA, A10
PRE/PALL
ILLEGAL
3
L
L
L
H
×
REF/SELF
ILLEGAL
L
L
L
L
Op-Code
MRS
ILLEGAL
Write recovering
H
×
×
×
×
DESL
Nop
→
Enter precharge after t
DPL
with auto precharge
L
H
H
H
×
NOP
Nop
→
Enter precharge after t
DPL
L
H
H
L
×
BST
Nop
→
Enter precharge after t
DPL
L
H
L
H
BA, CA, A10
READ/READA
ILLEGAL
3, 8
L
H
L
L
BA, CA, A10
WRIT/WRITA
ILLEGAL
3
L
L
H
H
BA, RA
ACT
ILLEGAL
3
L
L
H
L
BA, A10
PRE/PALL
ILLEGAL
L
L
L
H
×
REF/SELF
ILLEGAL
L
L
L
L
Op-Code
MRS
ILLEGAL
Refreshing
H
×
×
×
×
DESL
Nop
→
Enter idle after t
RC
L
H
H
×
×
NOP/BST
Nop
→
Enter idle after t
RC
L
H
L
×
×
READ/WRIT
ILLEGAL
L
L
H
×
×
ACT/PRE/PALL
ILLEGAL
L
L
L
×
×
REF/SELF/MRS
ILLEGAL
Mode register
H
×
×
×
×
DESL
Nop
→
Enter idle after t
RSC
accessing
L
H
H
H
×
NOP
Nop
→
Enter idle after t
RSC
L
H
H
L
×
BST
ILLEGAL
L
H
L
×
×
READ/WRIT
ILLEGAL
L
L
×
×
×
ACT/PRE/PALL/
REF/SELF/MRS
ILLEGAL
Notes 1.
All entries assume that CKE was active (High level) during the preceding clock cycle.
If all banks are idle, and CKE is inactive (Low level),
μ
PD4564323 will enter Power down mode.
All input buffers except CKE will be disabled.
Illegal to bank in specified states; Function may be legal in the bank indicated by Bank Address (BA),
depending on the state of that bank.
If all banks are idle, and CKE is inactive (Low level),
μ
PD4564323 will enter Self refresh mode. All input
buffers except CKE will be disabled.
Illegal if t
RCD
is not satisfied.
Illegal if t
RAS
is not satisfied.
Must satisfy burst interrupt condition.
Must satisfy bus contention, bus turn around, and/or write recovery requirements.
Must mask preceding data which don't satisfy t
DPL
.
Illegal if t
RRD
is not satisfied.
2.
3.
4.
5.
6.
7.
8.
9.
10.
Remark
H = High level, L = Low level,
×
= High or Low level (Don’t care), V = Valid data
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| UPD4564323G5-A10-9JH | 64M-bit Synchronous DRAM 4-bank, LVTTL |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| UPD4564323G5-A10BL-9HJ | 制造商:Renesas Electronics Corporation 功能描述: |
| UPD45D128442G5C759LG | 制造商:NEC 功能描述:* |
| UPD4701AC-A | 制造商:Renesas Electronics 功能描述:Cut Tape |
| UPD4702C-A | 制造商:Renesas Electronics 功能描述:Cut Tape |
| UPD4702G-A | 制造商:Renesas Electronics 功能描述:Cut Tape |
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