參數(shù)資料
型號(hào)： UPD46128512-E10X
廠(chǎng)商： NEC Corp.
英文描述： 128M-BIT CMOS MOBILE SPECIFIED RAM 8M-WORD BY 16-BIT EXTENDED TEMPERATURE OPERATION
中文描述： 128兆位CMOS移動(dòng)指明內(nèi)存800萬(wàn)字由16位溫度范圍
文件頁(yè)數(shù)： 6/82頁(yè)
文件大?。?/td> 817K
代理商： UPD46128512-E10X
Preliminary Data Sheet M17507EJ2V0DS
6
μ
PD46128512-X
Burst Operation
Mode
/CE1
CE2
CLK
/ADV
/OE
/WE
/LB
/UB
DQ
/WAIT
DQ0 to DQ7
DQ8 to DQ15
Note8
Not selected (Standby Mode 1)
H
H
×
×
×
×
×
×
High-Z
High-Z
High-Z
Not selected (Standby Mode 2)
Note1
×
L
×
×
×
×
×
×
High-Z
High-Z
High-Z
Start address latch
L
H
Note4
L
×
Note7
×
Note7
×
Note9
×
Note9
High-Z
Note5
High-Z
Note5
×
Advanced burst read to next address
H
L
H
D
OUT
D
OUT
Output
Note4
Valid
Burst read suspend
Note2
H
High-Z
High-Z
HIGH
Burst read resume
Note2
L
D
OUT
D
OUT
HIGH
Burst read termination
Note3
×
×
High-Z
High-Z
High-Z
Advanced burst write to next address
L
H
L
D
IN
D
IN
Output
Note4
Valid
Burst write suspend
Note2
H
High-Z
High-Z
HIGH
Burst write resume
Note2
L
D
IN
D
IN
HIGH
Burst write termination
Note3
×
×
High-Z
High-Z
High-Z
Abort write
Note6
L
×
×
Note10
HIGH
HIGH
High-Z
High-Z
HIGH
Notes 1.
CE2 pin must be fixed HIGH except Standby Mode 2 (refer to
2.3 Standby Mode Status Transition
).
Be sure to suspend or resume a burst read after outputting the first read access data.
Be sure to suspend or resume a burst write after latching the first write data.
Burst write suspend or resume is available when setting WC = 1 (/WE level control) through Mode Register
Set.
/
CE1 must be fixed HIGH during t
TRB
specification until next read or write operation.
Valid clock edge shall be set either positive or negative edge through Mode Register Set.
If /OE = LOW and /LB = /UB = LOW, output is valid. If /OE = LOW and /LB = /UB = HIGH, output is high
impedance.
If /WE = LOW, output is high impedance. If /OE = /WE = HIGH, output is high impedance.
If /WE = LOW and /LB = /UB = HIGH, memory does not accept write data, so write operation is not
available.
Both of two pins (/OE and /WE) or either of two should be connected to HIGH. It is prohibited to bring the
both /OE and /WE to LOW.
Refer to the
4.10 /WAIT
.
For the Burst Read, the /UB, /LB setup time to CLK (t
BC
) must be satisfied. For the Burst Write, the /UB,
/LB setup time to CLK (t
BC
) must be satisfied. Once /LB and /UB inputs are determined, they must not be
changed until the end of burst operation.
10.
In case of WC = 0, /WE is HIGH.
In case of WC = 1, /WE is LOW.
The explanation of WC refers to
Table 5-2. Mode Register Definition (5th Bus Cycle)
and
5.9 /WE
control
.
2.
3.
4.
5.
6.
7.
8.
9.
Remark
H, HIGH : V
IH
, L, LOW : V
IL
,
×
: V
IH
or V
IL
,
: valid edge
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